Abstract: Microbolometer circuitry and methods are disclosed to allow an individual microbolometer or groups of microbolometers, such as a microbolometer focal plane array, to operate over a wide temperature range. Temperature compensation is provided, such as through circuitry and/or calibration methods, to reduce non-uniform behavior over the desired operating temperatures. For example, the relative mismatch in the temperature coefficient of resistance of an active microbolometer and a reference microbolometer is compensated by employing a variable resistor in series with the active microbolometer. The variable resistor can be calibrated over the desired temperature range to minimize the affect of the relative mismatch. Various other circuit implementations, calibration methods, and processing of the microbolometer circuit output can be employed to provide further compensation.

Abstract: Systems and methods for microbolometer focal plane arrays are disclosed. For example, in accordance with an embodiment of the present invention, microbolometer focal plane array circuitry is disclosed for a microbolometer array having shared contacts between adjacent microbolometers. Various techniques may be applied to compensate for non-uniformities, such as for example, to allow operation over a calibrated temperature range.

Abstract: Two-stage auto-zero amplifier circuits are disclosed, along with methods of auto-zeroing such amplifier circuits. The two-stage auto-zero amplifier circuit may be part of an electronics signal chain coupled to a detector element to process an electronic signal induced by illumination. In an exemplary embodiment, the auto-zero amplifier circuit includes a first stage, which includes a low-noise fixed gain amplifier, capacitively coupled to a second stage, which includes a high gain amplifier. In an exemplary embodiment of a method of auto-zeroing the two-stage auto-zero amplifier circuit, a first terminal of the detector element is decoupled from the auto-zero amplifier circuit, and the first stage of the auto-zero amplifier circuit is locally referenced to a second terminal of the detector element. An auto-zero voltage for the auto-zero amplifier circuit is stored between the first stage of the auto-zero amplifier circuit and the second stage of the auto-zero amplifier circuit.

Abstract: Systems and methods are disclosed for measuring a distance (or gap) between substrates of a hybrid semiconductor. The measurements may be made during a hybridization process to, for example, provide alignment feedback during the hybridization process. The measurements may also be made after the hybridization process to further calibrate the process or to provide information useful for further processing operations.

Abstract: Microbolometer circuitry and methods are disclosed to allow an individual microbolometer or groups of microbolometers, such as a microbolometer focal plane array, to operate over a wide temperature range. Temperature compensation is provided, such as through circuitry and/or calibration methods, to reduce non-uniform behavior over the desired operating temperatures. For example, the relative mismatch in the temperature coefficient of resistance of an active microbolometer and a reference microbolometer is compensated by employing a variable resistor in series with the active microbolometer. The variable resistor can be calibrated over the desired temperature range to minimize the affect of the relative mismatch. Various other circuit implementations, calibration methods, and processing of the microbolometer circuit output can be employed to provide further compensation.

Abstract: An electro-optical sensor includes a detector pixel including a plurality of detector elements responsive to electromagnetic radiation, and a plurality of switches configurable to selectively combine signals from the detector elements in the detector pixel to provide a signal corresponding to a pixel in an image. The sensor may include a plurality of such detector pixels arranged, for example, in a linear array or in a two-dimensional array. Each of the detector pixels may have an associated group of switches configurable to selectively combine signals from the detector elements in the detector pixel.

Abstract: Methods of forming arrays of electrical interconnects between substrates are provided. These methods allow the use of large interconnect bump arrays to physically and electrically connect substrates without the need to use excess pressure on the substrates to form the interconnects, thus reducing damage to the substrates. To form the interconnects, an array of bumps is formed on a first substrate from a material that forms a eutectic composition with a second material. An array of bumps composed of the second material is formed on the second substrate. The arrays are aligned and the bumps contacted at a temperature above the eutectic temperature of the eutectic composition. Each of the bumps on the first substrate melts and diffuises into the corresponding bumps on the second substrate to form the interconnects.

Abstract: A differential current mode amplifier circuit (5,5′) includes a first circuit leg having a first current source providing a current I1 coupled in series with a first transistor (m1) at a first circuit node (n1). The first transistor has a control terminal for coupling to an input signal potential (Vs). Vs is obtained from a unit cell of a radiation detector array, and is indicative of a magnitude of an integrated, photon-induced charge. The first circuit leg outputs a first output current (Is). A second circuit leg includes a second current source providing a current I2 coupled in series with a second transistor (m2) at a second circuit node (n2). The second transistor has a control terminal for coupling to an input reference potential (Vr). The second circuit leg outputs a second output current (Ir). A resistance (Rs) is coupled between the first circuit leg and the second circuit leg at the first circuit node and the second node.

Abstract: A dual sample-and-hold architecture in each unit cell of a read-in-integrated-circuit (RIIC) provides maximum frame rate without frame overlap. Analog pixel signals are updated sequentially in one sample-and-hold capacitor, while an emitter element displays a pixel of a display frame in response to a stored analog signal voltage on an isolated second sample-and-hold capacitor. After all unit cells are updated, the signals on the two capacitors are combined, updating all emitter elements for the next frame. A voltage mode amplifier as an emitter driver provides a more nearly linear dependence of infrared power output on signal voltage than do previous transconductance amplifiers. A digital to analog converter (DAC) on the RIIC substrate results in a simplified interface to the RIIC and in an increased immunity to noise.

Abstract: A charge transfer structure (30) includes a substrate comprised of semiconductor material and, coupled to a surface of the substrate, a plurality of serially coupled devices each having a gate terminal. The plurality of serially coupled devices include a first single port device (D1) defining a first primary charge storage well, a second single port device (D3) defining a second primary charge storage well, a first two port device (D2) defining a first transfer device, a second two port device (D4) defining a second transfer device, and two instances of a third two port device each defining a cascode device (CD). The ports of these devices are serially coupled together in an order given by D1, D2, CD, D3, D4, CD for transferring charge between the first and second primary charge storage wells. Charge is inserted into and withdrawn from each of the first and second primary charge storage wells through a single diffusion that functions as both an input port and an output port.

Abstract: Correction for temperature-induced non-uniformities in the response characteristics of the microbolometers in an infrared focal plane array (FPA) is performed by applying a non-uniform corrective bias to the individual microbolometers. The corrective bias is applied either before or during the bias or integration period during which the detectors are sampled. The bias-correction can be applied to two-dimensional detector multiplexers at each column amplifier input, the reference potential for each column amplifier or the voltage supply for each detector element. The magnitude of each corrective bias is determined by calibrating the detectors at different temperatures and different levels of incident infrared radiation. According to another aspect of this invention, a microbolometer which is thermally-shorted to the substrate on which the read out integrated circuit (ROIC) is formed is used along with the sensing microbolometer to compensate for variations in temperature.

Abstract: Correction for temperature-induced non-uniformities in the response characteristics of the microbolometers in an infrared focal plane array (FPA) is performed by applying a non-uniform corrective bias to the individual microbolometers. The corrective bias is applied either before or during the bias or integration period during which the detectors are sampled. The bias-correction can be applied to two-dimensional detector multiplexers at each column amplifier input, the reference potential for each column amplifier or the voltage supply for each detector element. The magnitude of each corrective bias is determined by calibrating the detectors at different temperatures and different levels of incident infrared radiation. According to another aspect of this invention, a microbolometer which is thermally-shorted to the substrate on which the read out integrated circuit (ROIC) is formed is used along with the sensing microbolometer to compensate for variations in temperature.

Abstract: An integrated circuit analog-to-digital converter for use on the focal plane of an infrared detector array. The analog-to-digital converter has a sample and hold circuit, a comparator circuit, and a latch circuit. A single slope conversion technique is used to generate digital signals representative of the amplitude of the input analog signal.

Abstract: A wafer scale test system for testing redundant integrated circuit dies formed on a semiconductor wafer includes wafer scale test pads formed on the wafer and interchip multiplexor means for directing test signals applied to the wafer scale test pads to the individual integrated circuit dies. The interchip multiplexor means includes an input/output buffer circuit for receiving test signals from the wafer pads and applying the test signals to selected interchip multiplexor lines routed to the individual circuit dies. Readouts from output pads on said integrated circuit dies are routed back through the input/output buffer circuit to the wafer test pads to provide test output signals. Low cross-section connecting means are provided across dicing lanes between the integrated circuit die contact pads and the interchip multiplexor lines to avoid shorting during the dicing operation.

Abstract: A digitally programmable gain normalization circuit for normalizing gains among analog signal channels. The gain normalization circuit is comprised of a charge integrator which has a plurality of capacitors to provide selectible capacitance values which determine the gain of a differential amplifier/sample and hold circuit. A programmable gain control register selects the charge integrator capacitance value. Both static and dynamic latches are disclosed for selecting the capacitors to be utilized in the charge integrator.

Abstract: A wafer scale test system for testing redundant integrated circuit dies formed on a semiconductor wafer includes wafer scale test pads formed on the wafer and interchip multiplexor means for directing test signals applied to the wafer scale test pads to the individual integrated circuit dies. The interchip multiplexor means includes an input/output buffer circuit for receiving test signals from the wafer pads and applying the test signals to selected interchip multiplexor lines routed to the individual circuit dies. Readouts from output pads on said integrated circuit dies are routed back through the input/output buffer circuit to the wafer test pads to provide test output signals. Low cross-section connecting means are provided across dicing lanes between the integrated circuit die contact pads and the interchip multiplexor lines to avoid shorting during the dicing operation.

Abstract: A method and circuit are provided for interfacing an infrared detector to a common power supply and signal processing circuitry. A multichannel input circuit including a plurality of buffer circuits and a common bias network is formed on a single semiconductor substrate. The common bias network reduces the necessary connections between the substrate and the external power supply. The bias network is operative to reduce power level variations in the signal from the external power supply. Each channel includes a negative feedback circuit to maintain a dedicated detector in a zero bias condition, thus reducing 1/f noise and enhancing the signal-to-noise ratio of the circuit. The load to each channel is adjustable to maintain the detector in the zero bias condition.

Abstract: An open circuit photodiode includes a capacitor plate formed monolithically with a forward biased P-N junction diode. The capacitor plate, together with one side of the P-N junction, forms a capacitor which is charged by the photocurrent of the diode. The voltage across the capacitor controls the output current of a charge coupled device (CCD) register. The invention operates in an open circuit configuration so that no net current flows across the diode junction as long as the flux of incident radiation is constant. If the incident radiation flux changes, current flows across the diode junction so that the capacitor is charged (or discharged) to a new voltage level corresponding to the new radiation flux level. As a result, the open circuit voltage of the capacitor modulates as a function of the change in incident radiation flux.

Abstract: This invention improves production yield and charge transfer speed and efficiency at the detector/register interface in a focal plane array and includes a novel meander channel CCD serial register in which charge packets generated in the array are stored. The electrode edge length across which charge is transferred at each entrance to the serial register is substantially increased in this invention in comparison with the prior art, resulting in a significant improvement in charge transfer efficiency and layout simplicity. Furthermore, this invention provides symmetrical surface potential distribution, and eliminates the gap instability in charge transfer.

Abstract: A meander channel charge couple device having a pair of parallel colinear elongate electrodes extending longitudinally along the length of the register disposed over a meander channel and formed in the same conductive layer so that they both reside at the same height above the semiconductor substrate, thereby providing a symmetrical surface potential distribution. Charge transfer instabilities beneath a gap separating the electrodes are eliminated by providing an additional set of electrodes, each extending transversely to the meander channel and to the first pair of parallel electrodes and spanning the gap. Contact is made by each of the longitudinal electrode pairs to alternate ones of the transverse electrodes and a two-phase clock system is applied to the longitudinal electrode pair.