Patents by Inventor William J. Rudik
William J. Rudik has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 7615477Abstract: Ball Grid Array packages having decreased adhesion of the BGA pad to the laminate surface and methods for producing same are provided.Type: GrantFiled: December 5, 2006Date of Patent: November 10, 2009Assignee: International Business Machines CorporationInventors: John U. Knickerbocker, Voya R. Markovich, Thomas R. Miller, William J. Rudik
-
Patent number: 7547577Abstract: A method of making a circuitized substrate assembly in which two or more subassemblies are aligned and bonded together. The bonding, preferably using lamination, results in effective electrical connections being formed between respective pairs of conductors of the subassemblies in such a manner that the metallurgies of the conductors, and those of an interim metallic solder paste, are effectively mixed and the flowable interim dielectric used between the mating subassemblies is forced to flow to engage and surround the conductor coupling, without adversely affecting the electrical connection formed.Type: GrantFiled: November 14, 2006Date of Patent: June 16, 2009Assignee: Endicott Interconnect Technologies, Inc.Inventors: Norman A. Card, Thomas R. Miller, William J. Rudik
-
Publication number: 20080110016Abstract: A method of making a circuitized substrate assembly in which two or more subassemblies are aligned and bonded together. The bonding, preferably using lamination, results in effective electrical connections being formed between respective pairs of conductors of the subassemblies in such a manner that the metallurgies of the conductors, and those of an interim metallic solder paste, are effectively mixed and the flowable interim dielectric used between the mating subassemblies is forced to flow to engage and surround the conductor coupling, without adversely affecting the electrical connection formed.Type: ApplicationFiled: November 14, 2006Publication date: May 15, 2008Applicant: Endicott Interconnect Technologies, Inc.Inventors: Norman A. Card, Thomas R. Miller, William J. Rudik
-
Patent number: 7148566Abstract: Ball Grid Array packages having decreased adhesion of the BGA pad to the laminate surface and methods for producing same are provided.Type: GrantFiled: March 26, 2001Date of Patent: December 12, 2006Assignee: International Business Machines CorporationInventors: John U. Knickerbocker, Voya R. Markovich, Thomas R. Miller, William J. Rudik
-
Patent number: 6845557Abstract: A method for creating an impedance controlled printing wiring board, particularly the formation of a structure for high speed printed wiring boards incorporating multiple differential impedance controlled layers. Furthermore, disclosed is the provision of a method for producing an impedance controlled printed circuit wiring board. Also, there is the provision of a method for producing high speed printed wiring boards with multiple differential impedance controlled layers.Type: GrantFiled: August 22, 2002Date of Patent: January 25, 2005Assignee: International Business Machines CorporationInventors: Thomas R. Miller, William J. Rudik, Robert J. Testa, Kevin P. Unger, Michael Wozniak
-
Patent number: 6834426Abstract: A method for fabricating a laminate circuit structure is provided. The method comprises: providing at least two modularized circuitized voltage plane subassemblies wherein each of the subassemblies comprise at least two signal planes having an external and internal surface disposed about an internal voltage plane; providing a dielectric material between the signal and voltage planes; and providing dielectric on each external surface of each signal plane; and providing a non-cured or partially cured curable dielectric composition between the subassemblies wherein the dielectric composition comprises, dielectric material that is of the same material as the dielectric material used in said subassemblies, aligning the subassemblies, and then laminating to cause bonding of the subassemblies.Type: GrantFiled: July 25, 2000Date of Patent: December 28, 2004Assignee: International Business Machines CorporationInventors: Robert M. Japp, Gregory A. Kevern, William J. Rudik
-
Patent number: 6781064Abstract: A printed circuit board for use in an electronic device package such as a ball grid array package or organic chip carrier package. This printed circuit board includes a glass-free dielectric for separating and insulating power cores, circuitry or plated through holes from each other to prevent shorts caused by a migration of conductive material along glass-based prepreg substrates.Type: GrantFiled: June 29, 1999Date of Patent: August 24, 2004Assignee: International Business Machines CorporationInventors: Bernd K. Appelt, Anilkumar C. Bhatt, James W. Fuller, Jr., John M. Lauffer, Voya R. Markovich, William J. Rudik, William E. Wilson
-
Patent number: 6699736Abstract: A method and structure for conductively coupling a metallic stiffener to a chip carrier. A substrate has a conductive pad on its surface and an adhesive layer is formed on the substrate surface. The metallic stiffener is placed on the adhesive layer, wherein the adhesive layer mechanically couples the stiffener to the substrate surface and electrically couples the stiffener to the pad. The adhesive layer is then cured such as by pressurization at elevated temperature. Embodiments of the present invention form the adhesive layer by forming an electrically conductive contact on the pad and setting a dry adhesive on the substrate, such that the electrically conductive contact is within a hole in the dry adhesive. The electrically conductive contact electrically couples the stiffener to the pad. The curing step includes curing both the dry adhesive and the electrically conductive contact, resulting in the dry adhesive adhesively coupling the stiffener to the substrate.Type: GrantFiled: November 26, 2002Date of Patent: March 2, 2004Assignee: International Business Machines CorporationInventors: Terry J. Dornbos, Raymond A. Phillips, Jr., Mark V. Pierson, William J. Rudik, David L. Thomas
-
Patent number: 6639638Abstract: A large liquid crystal display optical structure can be created by providing a transparent substrate with a dark mesh pattern disposed thereon. A means for optical scattering is over, adjacent, or surrounding the dark mesh, with a polarizer laminated to a smooth surface of the means for optical scattering.Type: GrantFiled: August 27, 1999Date of Patent: October 28, 2003Assignee: International Business Machines CorporationInventors: Ramesh R. Kodnani, Mark V. Pierson, William J. Rudik, David B. Stone
-
Publication number: 20030082853Abstract: A method and structure for conductively coupling a metallic stiffener to a chip carrier. A substrate has a conductive pad on its surface and an adhesive layer is formed on the substrate surface. The metallic stiffener is placed on the adhesive layer, wherein the adhesive layer mechanically couples the stiffener to the substrate surface and electrically couples the stiffener to the pad. The adhesive layer is then cured such as by pressurization at elevated temperature. Embodiments of the present invention form the adhesive layer by forming an electrically conductive contact on the pad and setting a dry adhesive on the substrate, such that the electrically conductive contact is within a hole in the dry adhesive. The electrically conductive contact electrically couples the stiffener to the pad. The curing step includes curing both the dry adhesive and the electrically conductive contact, resulting in the dry adhesive adhesively coupling the stiffener to the substrate.Type: ApplicationFiled: November 26, 2002Publication date: May 1, 2003Inventors: Terry J. Dornbos, Raymond A. Phillips, Mark V. Pierson, William J. Rudik, David L. Thomas
-
Patent number: 6534848Abstract: A method and structure for conductively coupling a metallic stiffener to a chip carrier. A substrate has a conductive pad on its surface and an adhesive layer is formed on the substrate surface. The metallic stiffener is placed on the adhesive layer, wherein the adhesive layer mechanically couples the stiffener to the substrate surface and electrically couples the stiffener to the pad. The adhesive layer is then cured such as by pressurization at elevated temperature. Embodiments of the present invention form the adhesive layer by forming an electrically conductive contact on the pad and setting a dry adhesive on the substrate, such that the electrically conductive contact is within a hole in the dry adhesive. The electrically conductive contact electrically couples the stiffener to the pad. The curing step includes curing both the dry adhesive and the electrically conductive contact, resulting in the dry adhesive adhesively coupling the stiffener to the substrate.Type: GrantFiled: September 7, 2000Date of Patent: March 18, 2003Assignee: International Business Machines CorporationInventors: Terry J. Dornbos, Raymond A. Phillips, Jr., Mark V. Pierson, William J. Rudik, David L. Thomas
-
Publication number: 20020189094Abstract: A method for creating an impedance controlled printing wiring board, particularly the formation of a structure for high speed printed wiring boards incorporating multiple differential impedance controlled layers. Furthermore, disclosed is the provision of a method for producing an impedance controlled printed circuit wiring board. Also, there is the provision of a method for producing high speed printed wiring boards with multiple differential impedance controlled layers.Type: ApplicationFiled: August 22, 2002Publication date: December 19, 2002Applicant: International Business Machines CorporationInventors: Thomas R. Miller, William J. Rudik, Robert J. Testa, Kevin P. Unger, Michael Wozniak
-
Patent number: 6469256Abstract: A method for creating an impedance controlled printing wiring board, particularly the formation of a structure for high speed printed wiring boards incorporating multiple differential impedance controlled layers. Furthermore, disclosed is the provision of a method for producing an impedance controlled printed circuit wiring board. Also, there is the provision of a method for producing high speed printed wiring boards with multiple differential impedance controlled layers.Type: GrantFiled: February 1, 2000Date of Patent: October 22, 2002Assignee: International Business Machines CorporationInventors: Thomas R. Miller, William J. Rudik, Robert J. Testa, Kevin P. Unger, Michael Wozniak
-
Publication number: 20020137256Abstract: Ball Grid Array packages having decreased adhesion of the BGA pad to the laminate surface and methods for producing same are provided.Type: ApplicationFiled: March 26, 2001Publication date: September 26, 2002Applicant: International Business Machines CorporationInventors: John U. Knickerbocker, Voya R. Markovich, Thomas R. Miller, William J. Rudik
-
Patent number: 6399896Abstract: Reliability of circuit packaging while accommodating larger chips and increased temperature excursions is achieved by use of compliant pads only at the locations of connections between packaging levels, preferably between a laminated chip carrier and a printed circuit board. The invention allows the coefficient of thermal expansion of the chip carrier to be economically well-matched to the CTE of the chip and accommodation of significant differences in CTEs of package materials to be accommodated at a single packaging level. The compliant pads are preferably of low aspect ratio which are not significantly deflected by accelerations and can be formed on a surface or recessed into it. Connections can be made through surface connections and/or plated through holes. Connection enhancements such as solder wettable surfaces or dendritic textures are provided in a conductive metal or alloy layer over a compliant rubber or elastomer layer which may be conductive or non-conductive.Type: GrantFiled: March 15, 2000Date of Patent: June 4, 2002Assignee: International Business Machines CorporationInventors: Frank J. Downes, Jr., Donald S. Farquhar, Robert M. Japp, William J. Rudik
-
Patent number: 6348738Abstract: A method for forming a flip-chip-on-board assembly. An integrated circuit (IC) chip having a polyimide passivation layer is joined to a chip carrier via a plurality of solder bumps which electrically connect a plurality of contact pads on the IC chip to corresponding contacts on the chip carrier. A space is formed between a surface of the passivation layer and a surface of the chip carrier. A plasma is applied, to chemically modify the surface of the chip carrier and the passivation layer of the IC chip substantially without roughening the surface of the passivation layer. The plasma is either an O2 plasma or a microwave-generated Ar and N2O plasma. An underfill encapsulant material is applied to fill the space. The plasma treatment may be performed after the step of joining. Then, the chip and chip carrier are treated with the plasma simultaneously. Alternatively, the IC chip and chip carrier may be treated with the plasma before they are joined to one another.Type: GrantFiled: August 11, 1999Date of Patent: February 19, 2002Assignee: International Business Machines CorporationInventors: Jean Dery, Frank D. Egitto, Luis J. Matienzo, Charles Ouellet, Luc Ouellet, David L. Questad, William J. Rudik, Son K. Tran
-
Patent number: 6306683Abstract: A method for forming a flip-chip-on-board assembly. An integrated circuit (IC) chip having a polyimide passivation layer is joined to a chip carrier via a plurality of solder bumps which electrically connect a plurality of contact pads on the IC chip to corresponding contacts on the chip carrier. A space is formed between a surface of the passivation layer and a surface of the chip carrier. A plasma is applied, to chemically modify the surface of the chip carrier and the passivation layer of the IC chip substantially without roughening the surface of the passivation layer. The plasma is either an O2 plasma or a microwave-generated Ar and N2O plasma. An underfill encapsulant material is applied to fill the space. The plasma treatment may be performed after the step of joining. Then, the chip and chip carrier are treated with the plasma simultaneously. Alternatively, the IC chip and chip carrier may be treat with the plasma before they are joined to one another.Type: GrantFiled: March 16, 2000Date of Patent: October 23, 2001Assignee: International Business Machines CorporationInventors: Jean Dery, Frank D. Egitto, Luis J. Matienzo, Charles Ouellet, Luc Ouellet, David L. Questad, William J. Rudik, Son K. Tran
-
Patent number: 6074895Abstract: A method for forming a flip-chip-on-board assembly. An integrated circuit (IC) chip having a polyimide passivation layer is joined to a chip carrier via a plurality of solder bumps which electrically connect a plurality of contact pads on the IC chip to corresponding contacts on the chip carrier. A space is formed between a surface of the passivation layer and a surface of the chip carrier. A plasma is applied, to chemically modify the a surface of the chip carrier and the passivation layer of the IC chip substantially without roughening the surface of the passivation layer. The plasma is either an O.sub.2 plasma or a microwave-generated Ar and N.sub.2 O plasma. An underfill encapsulant material is applied to fill the space. The plasma treatment may be performed after the step of joining. Then, the chip and chip carrier are treated with the plasma simultaneously. Alternatively, the IC chip and chip carrier may be treated with the plasma before they are joined to one another.Type: GrantFiled: September 23, 1997Date of Patent: June 13, 2000Assignee: International Business Machines CorporationInventors: Jean Dery, Frank D. Egitto, Luis J. Matienzo, Charles Ouellet, Luc Ouellet, David L. Questad, William J. Rudik, Son K. Tran
-
Patent number: 5126192Abstract: A flame retardant, low dielectric constant, controlled coefficient of thermal expansion, low cost prepreg material which includes randomly distributed silane coated hollow microspheres has been prepared by standard impregnation and lamination techniques. Laminates made of this prepreg can be drilled cleanly for through holes and can be used as a substrate for surface mounted devices.Type: GrantFiled: January 26, 1990Date of Patent: June 30, 1992Assignee: International Business Machines CorporationInventors: Leroy N. Chellis, Robert M. Japp, William J. Summa, William J. Rudik, David W. Wang
-
Patent number: 4855333Abstract: A high density dimensionally stable encapsulated wire circuit board and a method of making such a board is described. A photo-curable adhesive having a unique combination of rheological properties is utilized to bond insulated wires to a substrate. The unique combination of rheological properties of the adhesive used in the encapsulated wire circuit boards of this invention include a specified range of values for the Storage Shear Modulus and specified range of values for the Loss Angle ratio.A new photo-curable adhesive having these properties and a method of obtaining such an adhesive are also described.Type: GrantFiled: April 6, 1987Date of Patent: August 8, 1989Assignee: International Business Machines Corp.Inventors: William J. Rudik, George P. Schmitt, John F. Shipley