Abstract: A method and system for determining an initial architectural state for instruction trace reconstruction. Performance projections for processor systems and memory subsystems are important for a correct understanding of work loads within the system. An instruction trace is generally utilized to determine distribution of instructions, identification of register dependencies, branch path analyses and timing. One well-known technique for reconstructing an instruction trace can be accomplished by monitoring bus traffic to determine instruction addresses, data addresses and data during the trace. However, the initial architectural state (the state of all caches, buffers and registers) must be determined in order to accurately reconstruct an instruction trace. At least one cache within the processor system is divided into two portions, the content of that cache is invalidated and each cache entry thereafter is duplicated within each portion of the divided cache.

Abstract: A multiprocessor computer system comprises a plurality of processors, wherein each processor includes an execution unit, a program counter, a result buffer containing a plurality of entries, each entry being allocated to hold an output value of an instruction executed by the execution unit, and an operation counter containing an operation count that is incremented at least when an instruction storing an output value to the result buffer is executed by the execution unit. A particular entry allocated in the result buffer for a given output value is selected as a function of the operation count at the time the instruction generating that given output value is executed. Each processor further includes a decoder that extracts a processor identifier from an instruction to be executed that identifies one of the plurality of processors, wherein one or more input values of the instruction are retrieved from the result buffer of the identified processor.

Abstract: Performance projections for processor systems and memory subsystems are important for a correct understanding of work loads within the system. An instruction trace is generally utilized to determine distribution of instructions, identification of register dependencies, branch path analyses and timing. One well known technique for reconstructing an instruction trace can be accomplished by monitoring bus traffic to determine address traces, data addresses and data during the trace, if the initial architectural state is known. The difficulty in reconstructing an instruction trace from monitored bus traffic can be decreased substantially if more definitive information regarding the actual instruction sequence can be obtained.

Abstract: A method and system for instruction trace reconstruction utilizing performance monitor outputs and bus monitoring. Performance projections for processor systems and memory subsystems are important for a correct understanding of work loads within the system. An instruction trace is generally utilized to determine distribution of instructions, identification of register dependencies, branch path analyzes and timing. One well known technique for reconstructing an instruction trace can be accomplished by monitoring bus traffic to determine instruction addresses, data addresses and data during the trace, if the initial architectural state of the system is known. The difficulty in reconstructing an instruction trace from monitored bus traffic can be decreased substantially if more definitive information regarding the actual instruction sequence can be obtained.