Patents by Inventor William K. Henson
William K. Henson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20130087859Abstract: A device including a p-type semiconductor device and an n-type semiconductor device on a semiconductor substrate. The n-type semiconductor device includes a gate structure having a high-k gate dielectric. A carbon dopant in a concentration ranging from 1×1016 atoms/cm3 to 1×1021 atoms/cm3 is present at an interface between the high-k gate dielectric of the gate structure for the n-type semiconductor device and the semiconductor substrate. Methods of forming the aforementioned device are also disclosed.Type: ApplicationFiled: October 5, 2011Publication date: April 11, 2013Applicant: International Business Machines CorporationInventors: Yue Liang, Dechao Guo, William K. Henson, Shreesh Narasimha, Yanfeng Wang
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Patent number: 8354309Abstract: Multiple types of gate stacks are formed on a doped semiconductor well. A high dielectric constant (high-k) gate dielectric is formed on the doped semiconductor well. A metal gate layer is formed in one device area, while the high-k gate dielectric is exposed in other device areas. Threshold voltage adjustment oxide layers having different thicknesses are formed in the other device areas. A conductive gate material layer is then formed over the threshold voltage adjustment oxide layers. One type of field effect transistors includes a gate dielectric including a high-k gate dielectric portion. Other types of field effect transistors include a gate dielectric including a high-k gate dielectric portion and a first threshold voltage adjustment oxide portions having different thicknesses. Field effect transistors having different threshold voltages are provided by employing different gate dielectric stacks and doped semiconductor wells having the same dopant concentration.Type: GrantFiled: January 10, 2012Date of Patent: January 15, 2013Assignee: International Business Machines CorporationInventors: Brian J. Greene, Michael P. Chudzik, Shu-Jen Han, William K. Henson, Yue Liang, Edward P. Maciejewski, Myung-Hee Na, Edward J. Nowak, Xiaojun Yu
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Patent number: 8350341Abstract: Adjustment of a switching threshold of a field effect transistor including a gate structure including a Hi-K gate dielectric and a metal gate is achieved and switching thresholds coordinated between NFETs and PFETs by providing fixed charge materials in a thin interfacial layer adjacent to the conduction channel of the transistor that is provided for adhesion of the Hi-K material, preferably hafnium oxide or HfSiON, depending on design, to semiconductor material rather than diffusing fixed charge material into the Hi-K material after it has been applied. The greater proximity of the fixed charge material to the conduction channel of the transistor increases the effectiveness of fixed charge material to adjust the threshold due to the work function of the metal gate, particularly where the same metal or alloy is used for both NFETs and PFETs in an integrated circuit; preventing the thresholds from being properly coordinated.Type: GrantFiled: April 9, 2010Date of Patent: January 8, 2013Assignee: International Business Machines CorporationInventors: Michael P. Chudzik, William K. Henson, Unoh Kwon
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Patent number: 8318565Abstract: Methods for fabricating gate electrode/high-k dielectric gate structures having an improved resistance to the growth of silicon dioxide (oxide) at the dielectric/silicon-based substrate interface. In an embodiment, a method of forming a transistor gate structure comprises: incorporating nitrogen into a silicon-based substrate proximate a surface of the substrate; depositing a high-k gate dielectric across the silicon-based substrate; and depositing a gate electrode across the high-k dielectric to form the gate structure. In one embodiment, the gate electrode comprises titanium nitride rich in titanium for inhibiting diffusion of oxygen.Type: GrantFiled: March 11, 2010Date of Patent: November 27, 2012Assignee: International Business Machines CorporationInventors: Huiming Bu, Michael P. Chudzik, Wei He, William K. Henson, Siddarth A. Krishnan, Unoh Kwon, Naim Moumen, Wesley C. Natzle
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Publication number: 20120286374Abstract: Methods for fabricating gate electrode/high-k dielectric gate structures having an improved resistance to the growth of silicon dioxide (oxide) at the dielectric/silicon-based substrate interface. In an embodiment, a method of forming a transistor gate structure comprises: incorporating nitrogen into a silicon-based substrate proximate a surface of the substrate; depositing a high-k gate dielectric across the silicon-based substrate; and depositing a gate electrode across the high-k dielectric to form the gate structure. In one embodiment, the gate electrode comprises titanium nitride rich in titanium for inhibiting diffusion of oxygen.Type: ApplicationFiled: July 24, 2012Publication date: November 15, 2012Applicant: International Business Machines CorporationInventors: Huiming Bu, Michael P. Chudzik, Wei He, William K. Henson, Siddarth A. Krishnan, Unoh Kwon, Naim Moumen, Wesley C. Natzle
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Patent number: 8299570Abstract: An eFuse, includes: a substrate and an insulating layer disposed on the substrate; a first layer including a single crystal or polycrystalline silicon disposed on the insulating layer; a second layer including a single crystal or polycrystalline silicon germanium disposed on the first layer, and a third layer including a silicide disposed on the second layer. The Ge has a final concentration in a range of approximately five percent to approximately twenty-five percent.Type: GrantFiled: July 22, 2011Date of Patent: October 30, 2012Assignee: International Business Machines CorporationInventors: Deok-Kee Kim, Dureseti Chidambarrao, William K. Henson, Chandrasekharan Kothandaraman
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Patent number: 8268698Abstract: The present invention relates to a semiconductor-on-insulator (SOI) substrate having one or more device regions. Each device region comprises at least a base semiconductor substrate layer and a semiconductor device layer with a buried insulator layer located therebetween, while the semiconductor device layer is supported by one or more vertical insulating pillars. The vertical insulating pillars each preferably has a ledge extending between the base semiconductor substrate layer and the semiconductor device layer. The SOI substrates of the present invention can be readily formed from a precursor substrate structure with a “floating” semiconductor device layer that is spaced apart from the base semiconductor substrate layer by an air gap and is supported by one or more vertical insulating pillars. The air gap is preferably formed by selective removal of a sacrificial layer located between the base semiconductor substrate layer and the semiconductor device layer.Type: GrantFiled: March 1, 2011Date of Patent: September 18, 2012Assignee: International Business Machines CorporationInventors: William K. Henson, Dureseti Chidambarrao, Kern Rim, Hsingjen Wann, Hung Y. Ng
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Publication number: 20120214299Abstract: Adjustment of a switching threshold of a field effect transistor including a gate structure including a Hi-K gate dielectric and a metal gate is achieved and switching thresholds coordinated between NFETs and PFETs by providing fixed charge materials in a thin interfacial layer adjacent to the conduction channel of the transistor that is provided for adhesion of the Hi-K material, preferably hafnium oxide or HfSiON, depending on design, to semiconductor material rather than diffusing fixed charge material into the Hi-K material after it has been applied. The greater proximity of the fixed charge material to the conduction channel of the transistor increases the effectiveness of fixed charge material to adjust the threshold due to the work function of the metal gate, particularly where the same metal or alloy is used for both NFETs and PFETs in an integrated circuit; preventing the thresholds from being properly coordinated.Type: ApplicationFiled: May 3, 2012Publication date: August 23, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael P. Chudzik, William K. Henson, Unoh Kwon
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Publication number: 20120208337Abstract: A low energy surface is formed by a high temperature anneal of the surfaces of trenches on each side of a gate stack. The material of the semiconductor layer reflows during the high temperature anneal such that the low energy surface is a crystallographic surface that is at a non-orthogonal angle with the surface normal of the semiconductor layer. A lattice mismatched semiconductor material is selectively grown on the semiconductor layer to fill the trenches, thereby forming embedded lattice mismatched semiconductor material portions in source and drain regions of a transistor. The embedded lattice mismatched semiconductor material portions can be in-situ doped without increasing punch-through. Alternately, a combination of intrinsic selective epitaxy and ion implantation can be employed to form deep source and drain regions.Type: ApplicationFiled: April 26, 2012Publication date: August 16, 2012Applicants: GLOBALFOUNDRIES INC., INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Brian J. Greene, William K. Henson, Judson R. Holt, Michael D. Steigerwalt, Kuldeep Amarnath, Rohit Pal, Johan W. Weijtmans
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Patent number: 8232606Abstract: A high-k dielectric and metal gate stack with minimal overlap with an adjacent oxide isolation region and related methods are disclosed. One embodiment of the gate stack includes a high dielectric constant (high-k) dielectric layer, a tuning layer and a metal layer positioned over an active region defined by an oxide isolation region in a substrate, wherein an outer edge of the high-k dielectric layer, the tuning layer and the metal layer overlaps the oxide isolation region by less than approximately 200 nanometers. The gate stack and related methods eliminate the regrowth effect in short channel devices by restricting the amount of overlap area between the gate stack and adjacent oxide isolation regions.Type: GrantFiled: June 1, 2011Date of Patent: July 31, 2012Assignee: International Business Machines CorporationInventors: Michael P. Chudzik, William K. Henson, Renee T. Mo, Jeffrey Sleight
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Patent number: 8227870Abstract: A method and structure to scale metal gate height in high-k/metal gate transistors. A method includes forming a dummy gate and at least one polysilicon feature, all of which are formed from a same polysilicon layer and wherein the dummy gate is formed over a gate metal layer associated with a transistor. The method also includes selectively removing the dummy gate while protecting the at least one polysilicon feature. The method further includes forming a gate contact on the gate metal layer to thereby form a metal gate having a height that is less than half a height of the at least one polysilicon feature.Type: GrantFiled: February 2, 2012Date of Patent: July 24, 2012Assignee: International Business Machines CorporationInventors: Michael P. Chudzik, Ricardo A. Donaton, William K. Henson, Yue Liang
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Patent number: 8222673Abstract: A low energy surface is formed by a high temperature anneal of the surfaces of trenches on each side of a gate stack. The material of the semiconductor layer reflows during the high temperature anneal such that the low energy surface is a crystallographic surface that is at a non-orthogonal angle with the surface normal of the semiconductor layer. A lattice mismatched semiconductor material is selectively grown on the semiconductor layer to fill the trenches, thereby forming embedded lattice mismatched semiconductor material portions in source and drain regions of a transistor. The embedded lattice mismatched semiconductor material portions can be in-situ doped without increasing punch-through. Alternately, a combination of intrinsic selective epitaxy and ion implantation can be employed to form deep source and drain regions.Type: GrantFiled: June 8, 2010Date of Patent: July 17, 2012Assignees: International Business Machines Corporation, Globalfoundries Inc.Inventors: Brian J. Greene, William K. Henson, Judson R. Holt, Michael D. Steigerwalt, Kuldeep Amarnath, Rohit Pal, Johan W. Weijtmans
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Publication number: 20120126335Abstract: A method and structure to scale metal gate height in high-k/metal gate transistors. A method includes forming a dummy gate and at least one polysilicon feature, all of which are formed from a same polysilicon layer and wherein the dummy gate is formed over a gate metal layer associated with a transistor. The method also includes selectively removing the dummy gate while protecting the at least one polysilicon feature. The method further includes forming a gate contact on the gate metal layer to thereby form a metal gate having a height that is less than half a height of the at least one polysilicon feature.Type: ApplicationFiled: February 2, 2012Publication date: May 24, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael P. CHUDZIK, Ricardo A. DONATON, William K. HENSON, Yue LIANG
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Publication number: 20120104505Abstract: A method is provided that includes forming a high-k dielectric etch stop layer over at least a first conductivity type semiconductor device on a first portion of a substrate and at least a second conductivity type semiconductor device on a second portion of the semiconductor device. A first stress-inducing layer is deposited over the first conductivity type semiconductor device and the second conductivity type semiconductor device. The portion of the first stress-inducing layer that is formed over the second conductivity type semiconductor device is then removed with an etch that is selective to the high-k dielectric etch stop layer to provide an exposed surface of second portion of the substrates that includes at least the second conductivity type semiconductor device. A second stress-inducing layer is then formed over the second conductivity type semiconductor device.Type: ApplicationFiled: October 28, 2010Publication date: May 3, 2012Applicant: International Business Machines CorporationInventor: William K. Henson
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Publication number: 20120108017Abstract: Multiple types of gate stacks are formed on a doped semiconductor well. A high dielectric constant (high-k) gate dielectric is formed on the doped semiconductor well. A metal gate layer is formed in one device area, while the high-k gate dielectric is exposed in other device areas. Threshold voltage adjustment oxide layers having different thicknesses are formed in the other device areas. A conductive gate material layer is then formed over the threshold voltage adjustment oxide layers. One type of field effect transistors includes a gate dielectric including a high-k gate dielectric portion. Other types of field effect transistors include a gate dielectric including a high-k gate dielectric portion and a first threshold voltage adjustment oxide portions having different thicknesses. Field effect transistors having different threshold voltages are provided by employing different gate dielectric stacks and doped semiconductor wells having the same dopant concentration.Type: ApplicationFiled: January 10, 2012Publication date: May 3, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Brian J. Greene, Michael P. Chudzik, Shu-Jen Han, William K. Henson, Yue Liang, Edward P. Maciejewski, Myung-Hee Na, Edward J. Nowak, Xiaojun Yu
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Publication number: 20120091506Abstract: A semiconductor structure including a p-channel field effect transistor (pFET) device located on a surface of a silicon germanium (SiGe) channel is provided in which the junction profile of the source region and the drain region is abrupt. The abrupt source/drain junctions for pFET devices are provided in this disclosure by forming an N- or C-doped Si layer directly beneath a SiGe channel layer which is located above a Si substrate. A structure is thus provided in which the N- or C-doped Si layer (sandwiched between the SiGe channel layer and the Si substrate) has approximately the same diffusion rate for a p-type dopant as the overlying SiGe channel layer. Since the N- or C-doped Si layer and the overlying SiGe channel layer have substantially the same diffusivity for a p-type dopant and because the N- or C-doped Si layer retards diffusion of the p-type dopant into the underlying Si substrate, abrupt source/drain junctions can be formed.Type: ApplicationFiled: October 15, 2010Publication date: April 19, 2012Applicant: International Business Machines CorporationInventors: Kern Rim, William K. Henson, Yue Liang, Xinlin Wang
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Patent number: 8138037Abstract: A method and structure to scale metal gate height in high-k/metal gate transistors. A method includes forming a dummy gate and at least one polysilicon feature, all of which are formed from a same polysilicon layer and wherein the dummy gate is formed over a gate metal layer associated with a transistor. The method also includes selectively removing the dummy gate while protecting the at least one polysilicon feature. The method further includes forming a gate contact on the gate metal layer to thereby form a metal gate having a height that is less than half a height of the at least one polysilicon feature.Type: GrantFiled: March 2, 2010Date of Patent: March 20, 2012Assignee: International Business Machines CorporationInventors: Michael P. Chudzik, Ricardo A. Donaton, William K. Henson, Yue Liang
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Patent number: 8106455Abstract: Multiple types of gate stacks are formed on a doped semiconductor well. A high dielectric constant (high-k) gate dielectric is formed on the doped semiconductor well. A metal gate layer is formed in one device area, while the high-k gate dielectric is exposed in other device areas. Threshold voltage adjustment oxide layers having different thicknesses are formed in the other device areas. A conductive gate material layer is then formed over the threshold voltage adjustment oxide layers. One type of field effect transistors includes a gate dielectric including a high-k gate dielectric portion. Other types of field effect transistors include a gate dielectric including a high-k gate dielectric portion and a first threshold voltage adjustment oxide portions having different thicknesses. Field effect transistors having different threshold voltages are provided by employing different gate dielectric stacks and doped semiconductor wells having the same dopant concentration.Type: GrantFiled: April 30, 2009Date of Patent: January 31, 2012Assignee: International Business Machines CorporationInventors: Brian J. Greene, Michael P. Chudzik, Shu-Jen Han, William K. Henson, Yue Liang, Edward P. Maciejewski, Myung-Hee Na, Edward J. Nowak, Xiaojun Yu
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Publication number: 20110298008Abstract: A low energy surface is formed by a high temperature anneal of the surfaces of trenches on each side of a gate stack. The material of the semiconductor layer reflows during the high temperature anneal such that the low energy surface is a crystallographic surface that is at a non-orthogonal angle with the surface normal of the semiconductor layer. A lattice mismatched semiconductor material is selectively grown on the semiconductor layer to fill the trenches, thereby forming embedded lattice mismatched semiconductor material portions in source and drain regions of a transistor. The embedded lattice mismatched semiconductor material portions can be in-situ doped without increasing punch-through. Alternately, a combination of intrinsic selective epitaxy and ion implantation can be employed to form deep source and drain regions.Type: ApplicationFiled: June 8, 2010Publication date: December 8, 2011Applicants: GLOBALFOUNDRIES INC., INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Brian J. Greene, William K. Henson, Judson R. Holt, Michael D. Steigerwalt, Kuldeep Amarnath, Rohit Pal, Johan W. Weijtmans
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Publication number: 20110272779Abstract: An eFuse, includes: a substrate and an insulating layer disposed on the substrate; a first layer including a single crystal or polycrystalline silicon disposed on the insulating layer; a second layer including a single crystal or polycrystalline silicon germanium disposed on the first layer, and a third layer including a silicide disposed on the second layer. The Ge has a final concentration in a range of approximately five percent to approximately twenty-five percent.Type: ApplicationFiled: July 22, 2011Publication date: November 10, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Deok-Kee Kim, Dureseti Chidambarrao, William K. Henson, Chandrasekharan Kothandaraman