Patents by Inventor William Leong
William Leong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20040024217Abstract: In its several embodiments, this invention discloses novel processes to prepare the compounds of formula II and formula IV: 1Type: ApplicationFiled: March 27, 2003Publication date: February 5, 2004Applicant: Schering CorporationInventors: William Leong, Minzhang Chen, Bosco A. D'sa, Man Zhu, Tong Xiao, Xiongwei Shi, Suhan Tang, Dinesh Gala, Andrew J. Goodman, Christopher M. Nielsen, Gary M. Lee, Juan A. Gamboa, Andrew D. Jones
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Publication number: 20030139446Abstract: In one embodiment, the present invention discloses a process to directly prepare an unequal ratio of specific, preferred rotamer or rotameric pair of an acid salt from a basic compound, by creative choice of a solvent medium. The process is particularly useful in preparing desired rotamers of pharmaceutically useful salts.Type: ApplicationFiled: November 26, 2002Publication date: July 24, 2003Applicant: Schering CorporationInventors: Minzhang Chen, Bosco D'sa, William Leong, Suhan Tang
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Publication number: 20020130681Abstract: A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks (“LABs”). The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module with any other logic module. In addition, adjacent or nearby logic modules are connectable to one another for such special purposes as providing a carry chain between logic modules and/or for connecting two or more modules together to provide more complex logic functions without having to make use of the general interconnection network. Another network of so-called fast or universal conductors is provided for distributing widely used logic signals such as clock and clear signals throughout the circuit. Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors.Type: ApplicationFiled: August 22, 2001Publication date: September 19, 2002Inventors: Richard G. Cliff, L. Todd Cope, Cameron R. Mc Clintock, William Leong, James A. Watson, Joseph Huang, Bahram Ahanin
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Patent number: 6396304Abstract: A programmable logic array integrated circuit device has logic regions grouped in blocks, which are in turn grouped in super-blocks. The super-blocks are disposed on the device in a two-dimensional array of intersecting rows and columns. Global conductors are associated with each row and column. Super-block feeding conductors associated with each super-block feed signals from the global conductors to any logic region in the super-block. Local feedback conductors feed back logic region output signals to all logic regions in a block. The super-block feeding conductors are also used to interconnect the logic regions in a super-block so that the global conductors do not have to be used for that purpose.Type: GrantFiled: December 9, 1999Date of Patent: May 28, 2002Assignee: Altera CorporationInventors: Richard G. Cliff, Cameron McClintock, William Leong
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Publication number: 20010043083Abstract: A programmable logic array integrated circuit device has logic regions grouped in blocks, which are in turn grouped in super-blocks. The super-blocks are disposed on the device in a two-dimensional array of intersecting rows and columns. Global conductors are associated with each row and column. Super-block feeding conductors associated with each super-block feed signals from the global conductors to any logic region in the super-block. Local feedback conductors feed back logic region output signals to all logic regions in a block. The super-block feeding conductors are also used to interconnect the logic regions in a super-block so that the global conductors do not have to be used for that purpose.Type: ApplicationFiled: December 9, 1999Publication date: November 22, 2001Inventors: RICHARD G. CLIFF, CAMERON MCCLINTOCK, WILLIAM LEONG
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Patent number: 6278291Abstract: A programmable logic array device has a plurality of logic regions and conductors for conveying signals between the logic regions. Conductors of several different lengths are provided so that most connections between logic regions can be made using conductors which are close to the length required and not wastefully much longer than that length.Type: GrantFiled: July 21, 2000Date of Patent: August 21, 2001Assignee: Altera CorporationInventors: Cameron McClintock, William Leong, Richard G. Cliff, Bahram Ahanin
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Patent number: 6134173Abstract: A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks ("LABs"). The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module with any other logic module. In addition, adjacent or nearby logic modules are connectable to one another for such special purposes as providing a carry chain between logic modules and/or for connecting two or more modules together to provide more complex logic functions without having to make use of the general interconnection network. Another network of so-called fast or universal conductors is provided for distributing widely used logic signals such as clock and clear signals throughout the circuit. Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors.Type: GrantFiled: November 2, 1998Date of Patent: October 17, 2000Assignee: Altera CorporationInventors: Richard G. Cliff, L. Todd Cope, Cameron R. McClintock, William Leong, James A. Watson, Joseph Huang, Bahram Ahanin
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Patent number: 6128692Abstract: A programmable logic array integrated circuit device has a relatively large block of programmable memory cells in addition to the usual programmable logic modules and the usual programmable interconnection conductor network. In order to simplify the circuitry associated with the large block, and especially the circuitry for addressing that block during programming and/or verification of the device, the address decoder that is normally used to address the block during use of the device to perform logic is also used during programming and/or verification. During programming and/or verification a counter or other similar coded address signal generating circuitry is used to supply address information to the decoder.Type: GrantFiled: June 11, 1998Date of Patent: October 3, 2000Assignee: Altera CorporationInventors: Chiakang Sung, Wanli Chang, Joseph Huang, Richard G. Cliff, L. Todd Cope, William Leong, deceased, by Louis Leong, legal representative
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Patent number: 6127846Abstract: A programmable logic array device has a plurality of logic regions and conductors for conveying signals between the logic regions. Conductors of several different lengths are provided so that most connections between logic regions can be made using conductors which are close to the length required and not wastefully much longer than that length.Type: GrantFiled: December 21, 1998Date of Patent: October 3, 2000Assignee: Altera CorporationInventors: Cameron McClintock, William Leong, Richard G. Cliff, Bahram Ahanin
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Patent number: 6064599Abstract: A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks ("LABs") The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module with any other logic module. In addition, adjacent or nearby logic modules are connectable to one another for such special purposes as providing a carry chain between logic modules and/or for connecting two or more modules together to provide more complex logic functions without having to make use of the general interconnection network. Another network of so-called fast or universal conductors is provided for distributing widely used logic signals such as clock and clear signals throughout the circuit. Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors.Type: GrantFiled: October 26, 1998Date of Patent: May 16, 2000Assignee: Altera CorporationInventors: Richard G. Cliff, L. Todd Cope, Cameron R. Mc Clintock, William Leong, James A. Watson, Joseph Huang, Bahram Ahanin
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Patent number: 6028808Abstract: A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks ("LABs"). The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module with any other logic module. In addition, adjacent or nearby logic modules are connectable to one another for such special purposes as providing a carry chain between logic modules and/or for connecting two or more modules together to provide more complex logic functions without having to make use of the general interconnection network. Another network of so-called fast or universal conductors is provided for distributing widely used logic signals such as clock and clear signals throughout the circuit. Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors.Type: GrantFiled: May 6, 1997Date of Patent: February 22, 2000Assignee: Altera CorporationInventors: Richard G. Cliff, L. Todd Cope, Cameron R. Mc Clintock, William Leong, James A. Watson, Joseph Huang, Bahram Ahanin
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Patent number: 6023439Abstract: A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks ("LABs"). The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module with any other logic module. In addition, adjacent or nearby logic modules are connectable to one another for such special purposes as providing a carry chain between logic modules and/or for connecting two or more modules together to provide more complex logic functions without having to make use of the general interconnection network. Another network of so-called fast or universal conductors is provided for distributing widely used logic signals such as clock and clear signals throughout the circuit. Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors.Type: GrantFiled: September 17, 1998Date of Patent: February 8, 2000Assignee: Altera CorporationInventors: Richard G. Cliff, L. Todd Cope, Cameron R. McClintock, William Leong, James A. Watson, Joseph Huang, Bahram Ahanin
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Patent number: 6018490Abstract: A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks ("LABs"). The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module with any other logic module. In addition, adjacent or nearby logic modules are connectable to one another for such special purposes as providing a carry chain between logic modules and/or for connecting two or more modules together to provide more complex logic functions without having to make use of the general interconnection network. Another network of so-called fast or universal conductors is provided for distributing widely used logic signals such as clock and clear signals throughout the circuit. Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors.Type: GrantFiled: October 9, 1998Date of Patent: January 25, 2000Assignee: Altera CorporationInventors: Richard G. Cliff, L. Todd Cope, Cameron R. Mc Clintock, William Leong, James A. Watson, Joseph Huang, Bahram Ahanin
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Patent number: 5900743Abstract: A programmable logic array device has a plurality of logic regions and conductors for conveying signals between the logic regions. Conductors of several different lengths are provided so that most connections between logic regions can be made using conductors which are close to the length required and not wastefully much longer than that length.Type: GrantFiled: September 16, 1997Date of Patent: May 4, 1999Assignee: Altera CorporationInventors: Cameron McClintock, William Leong, Richard G. Cliff, Bahram Ahanin
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Patent number: 5883850Abstract: A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks ("LABs"). The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module with any other logic module. In addition, adjacent or nearby logic modules are connectable to one another for such special purposes as providing a carry chain between logic modules and/or for connecting two or more modules together to provide more complex logic functions without having to make use of the general interconnection network. Another network of so-called fast or universal conductors is provided for distributing widely used logic signals such as clock and clear signals throughout the circuit. Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors.Type: GrantFiled: June 18, 1996Date of Patent: March 16, 1999Assignee: Altera CorporationInventors: Fung Fung Lee, Richard G. Cliff, L. Todd Cope, Cameron R. McClintock, William Leong, James A. Watson, Joseph Huang, Bahram Ahanin
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Patent number: 5848005Abstract: A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks ("LABs"). The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module with any other logic module. In addition, adjacent or nearby logic modules are connectable to one another for such special purposes as providing a carry chain between logic modules and/or for connecting two or more modules together to provide more complex logic functions without having to make use of the general interconnection network. Another network of so-called fast or universal conductors is provided for distributing widely used logic signals such as clock and clear signals throughout the circuit. Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors.Type: GrantFiled: May 6, 1997Date of Patent: December 8, 1998Assignee: Altera CorporationInventors: Richard G. Cliff, L. Todd Cope, Cameron R. McClintock, William Leong, James A. Watson, Joseph Huang, Bahram Ahanin
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Patent number: 5838628Abstract: A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks ("LABs"). The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module with any other logic module. In addition, adjacent or nearby logic modules are connectable to one another for such special purposes as providing a carry chain between logic modules and/or for connecting two or more modules together to provide more complex logic functions without having to make use of the general interconnection network. Another network of so-called fast or universal conductors is provided for distributing widely used logic signals such as clock and clear signals throughout the circuit. Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors.Type: GrantFiled: April 22, 1997Date of Patent: November 17, 1998Assignee: Altera CorporationInventors: Richard G. Cliff, L. Todd Cope, Cameron R. Mc Clintock, William Leong, James A. Watson, Joseph Huang, Bahram Ahanin
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Patent number: 5828229Abstract: A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks ("LABs"). The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module with any other logic module. In addition, adjacent or nearby logic modules are connectable to one another for such special purposes as providing a carry chain between logic modules and/or for connecting two or more modules together to provide more complex logic functions without having to make use of the general interconnection network. Another network of so-called fast or universal conductors is provided for distributing widely used logic signals such as clock and clear signals throughout the circuit. Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors.Type: GrantFiled: May 1, 1997Date of Patent: October 27, 1998Assignee: Altera CorporationInventors: Richard G. Cliff, L. Todd Cope, Cameron McClintock, William Leong, James Allen Watson, Joseph Huang, Bahram Ahanin, Chiakang Sung, Wanli Chang
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Patent number: 5812479Abstract: A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks ("LABs"). The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module with any other logic module. In addition, adjacent or nearby logic modules are connectable to one another for such special purposes as providing a carry chain between logic modules and/or for connecting two or more modules together to provide more complex logic functions without having to make use of the general interconnection network. Another network of so-called fast or universal conductors is provided for distributing widely used logic signals such as clock and clear signals throughout the circuit. Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors.Type: GrantFiled: May 6, 1997Date of Patent: September 22, 1998Assignee: Altera CorporationInventors: Richard G. Cliff, L. Todd Cope, Cameron R. Mc Clintock, William Leong, James A. Watson, Joseph Huang, Bahram Ahanin
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Patent number: 5764583Abstract: A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks ("LABs"). The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module with any other logic module. In addition, adjacent or nearby logic modules are connectable to one another for such special purposes as providing a carry chain between logic modules and/or for connecting two or more modules together to provide more complex logic functions without having to make use of the general interconnection network. Another network of so-called fast or universal conductors is provided for distributing widely used logic signals such as clock and clear signals throughout the circuit. Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors.Type: GrantFiled: May 6, 1997Date of Patent: June 9, 1998Assignee: Altera CorporationInventors: Richard G. Cliff, L. Todd Cope, Cameron R. McClintock, William Leong, James A. Watson, Joseph Huang, Bahram Ahanin