Abstract: A programmable logic array integrated circuit device has regions of programmable logic grouped in blocks disposed on the device in a two-dimensional array of intersecting rows and columns. Each block includes a relatively small number of logic regions to reduce the size and complexity of the local feedback circuity required in the block. Interconnection conductors extend along each row and column of blocks. Some of these conductors are segmented along their length to permit independent use of each segment. When longer interconnections are required, however, adjacent segments can be interconnected by programmable bi-directional switches between the segments.

Abstract: A process for producing a hydrazide of the formula: ##STR1## is disclosed. The process comprises reacting a hydrazone of the formula: ##STR2## wherein said hydrazone is in toluene, with a mixture of Grignard reagents, wherein said Grignard reagents are in a suitable organic solvent; wherein: (A) Z is a suitable carbonyl protecting group; (B) R is a suitable --OH protecting group; (C) R.sup.1 is selected from: H, a non-enolizable alkyl, a non-enolizable substituted alkyl, aryl, substituted aryl, --S-aryl, --S-(substituted aryl), --S-alkyl, --S-(substituted alkyl), alkoxy, substituted alkoxy, aryloxy, or substituted aryloxy; (D) said mixture of Grignard reagents comprises R.sup.2 MgX in admixture with R.sup.3 MgX; (E) R.sup.2 is a suitable alkyl, substituted alkyl, alkenyl, alkynyl, aryl, substituted aryl, or aralkyl group capable of adding to the --C.dbd.N group of the hydrazone to produce the hydrazide; (F) R.sup.

Abstract: A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks ("LABs"). The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module with any other logic module. In addition, adjacent or nearby logic modules are connectable to one another for such special purposes as providing a carry chain between logic modules and/or for connecting two or more modules together to provide more complex logic functions without having to make use of the general interconnection network. Another network of so-called fast or universal conductors is provided for distributing widely used logic signals such as clock and clear signals throughout the circuit. Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors.

Abstract: Described is a process for preparing triazolone compounds of the formula ##STR1## comprising heating a mixture of a compound of the formula ##STR2## and a hydrazine derivative of the formula R.sup.5 --NH--NH--CHO, R.sup.5 --NH--NH--C(O)OC(CH.sub.3).sub.3 or R.sup.5 --NH--NH--C(O)OCH.sub.2 C.sub.6 H.sub.5, optionally in the presence of an added base.

Abstract: A programmable logic array integrated circuit device has regions of programmable logic grouped in blocks disposed on the device in a two-dimensional array of intersecting rows and columns. Each block includes a relatively small number of logic regions to reduce the size and complexity of the local feedback circuity required in the block. Interconnection conductors extend along each row and column of blocks. Some of these conductors are segmented along their length to permit independent use of each segment. When longer interconnections are required, however, adjacent segments can be interconnected by programmable bi-directional switches between the segments.

Abstract: A programmable logic array integrated circuit device has a plurality of programmable logic regions arranged in a two-dimensional array of intersecting rows and columns. Associated with each logic region in each row is a local feedback conductor that spans a unique plurality of other logic regions in the row. Each such local feedback conductor makes the output of the associated logic region available as a possible input to any of the logic regions spanned by that conductor. Each logic region also has several associated intermediary conductors for making the signals on longer leads (such as row-long leads) available as possible inputs to any of the logic regions spanned by the intermediary conductors. At least some of the intermediary conductors associated with each logic region span different groups of logic regions.

Abstract: A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks ("LABs"). The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module with any other logic module. In addition, adjacent or nearby logic modules are connectable to one another for such special purposes as providing a carry chain between logic modules and/or for connecting two or more modules together to provide more complex logic functions without having to make use of the general interconnection network. Another network of so-called fast or universal conductors is provided for distributing widely used logic signals such as clock and clear signals throughout the circuit. Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors.

Abstract: A programmable logic array device has a plurality of logic regions and conductors for conveying signals between the logic regions. Conductors of several different lengths are provided so that most connections between logic regions can be made using conductors which are close to the length required and not wastefully much longer than that length.

Abstract: A programmable logic array integrated circuit device has logic regions grouped in blocks, which are in turn grouped in super-blocks. The super-blocks are disposed on the device in a two-dimensional array of intersecting rows and columns. Global conductors are associated with each row and column. Super-block feeding conductors associated with each super-block feed signals from the global conductors to any logic region in the super-block. Local feedback conductors feed back logic region output signals to all logic regions in a block. The super-block feeding conductors are also used to interconnect the logic regions in a super-block so that the global conductors do not have to be used for that purpose.

Abstract: Described is a process for preparing chiral compounds of the formula ##STR1## wherein X.sup.1 and X.sup.2 are independently F or Cl, and Y is Cl, Br or I, comprising reacting a triol of the formula ##STR2## wherein X.sup.1 and X.sup.2 are as defined above, with acetone in the presence of a catalyst, then with a halogen selected from Cl.sub.2, Br.sub.2 or I.sub.2, or N-bromosuccinimide or N-iodosuccinimide.

Abstract: A programmable logic device has a number of dedicated global control input lines which interface directly with individual building blocks known as logic array blocks. These lines can be used for clocks, presets, clears, or output-enables. Other logic signal lines from the centrally located global interconnect array are selected through an array of multiplexers and then interface with the logic array block. A configuration array of multiplexers in the logic array block selects from among these inputs, generating local control input signals, the final functions of which are decided by further multiplexing at the macrocell level within the logic array block.

Abstract: A programmable logic device has a number of dedicated global control input lines which interface directly with individual building blocks known as logic array blocks. These lines can be used for clocks, presets, clears, or output-enables. Other logic signal lines from the centrally located global interconnect array are selected through an array of multiplexers and then interface with the logic array block. A configuration array of multiplexers in the logic array block selects from among these inputs, generating local control input signals, the final functions of which are decided by further multiplexing at the macrocell level within the logic array block.