Abstract: A circuit that reduces external terminal count of a semiconductor chip, such as a communications chip or other type of chip that requires the generation of configuration codes, by reducing the number of external input terminals required for generating the configuration data. The circuit includes multiplexers, each of which selects output data or configuration data, and includes an output in communication with a respective external output terminal of the chip. A selector is connectable between a selected one of the external output terminals and an external input terminal in communication with a memory to serially input configuration data on that output terminal to the memory to configure the chip. Thus, configuration codes are generated for the chip using a reduced number of external input terminals, thereby reducing the overall external terminal count of the chip. The circuit and chip may be embodied on a network or Ethernet card.

Abstract: A circuit that reduces external terminal count of a semiconductor chip, such as a communications chip or other type of chip that requires the generation of configuration codes, by reducing the number of external input terminals required for generating the configuration data. The circuit includes multiplexers, each of which selects output data or configuration data, and includes an output in communication with a respective external output terminal of the chip. A selector is connectable between a selected one of the external output terminals and an external input terminal in communication with a memory to serially input configuration data on that output terminal to the memory to configure the chip. Thus, configuration codes are generated for the chip using a reduced number of external input terminals, thereby reducing the overall external terminal count of the chip. The circuit and chip may be embodied on a network or Ethernet card.

Abstract: A circuit that reduces external terminal count of a semiconductor chip, such as a communications chip or other type of chip that requires the generation of configuration codes, by reducing the number of external input terminals required for generating the configuration data. The circuit includes multiplexers, each of which selects output data or configuration data, and includes an output in communication with a respective external output terminal of the chip. A selector is connectable between a selected one of the external output terminals and an external input terminal in communication with a memory to serially input configuration data on that output terminal to the memory to configure the chip. Thus, configuration codes are generated for the chip using a reduced number of external input terminals, thereby reducing the overall external terminal count of the chip. The circuit and chip may be embodied on a network or Ethernet card.

Abstract: A virtual interactive response (VIR) system mimics and enhances interactive voice response (IVR) technology by using humans to drive the voice recognition unit (VRU) speech recognition functionality. This VIR system initiates a dialogue with the customer by prompting the customer with an initial welcoming message. Calls from a customer are initially made in a first region having high labor costs, but are then directed to an overseas location using voice over Internet protocol (VOIP) or other voice communications technology. The calls are then directed to an appropriate human agent at the overseas location who then listens to the customer's query and makes a decision on how to respond to the customer.

Abstract: A physical layer device (PHY) device in an Ethernet LAN is configured to permit ease of testing of its transmitter logic. The PHY device comprises a reset extension circuit for latching on the clock signals from a phase-locked loop (PLL) after the PLL has stabilized upon power-up or reset. The PHY device transmits a known valid bit pattern for testing purposes. A signal analyzer receives the transmitted bit pattern from the PHY device and compares the received bit pattern with a known valid bit pattern. A match indicates the proper operation of the PHY device transmitter logic.

Abstract: A physical layer (PHY) device in an Ethernet type LAN is configured to permit ease of testing of the PHY device's logic. The PHY device comprises a PHY receiver, a start frame delimiter detector (SFD), and automatic checker circuitry in which the clock position and the PHY pop-up position of received signals can be determined. The automatic checker circuitry receives a data signal having a predetermined pattern corresponding to a valid data packet from a pattern generating circuit. The automatic checker circuitry outputs a verification signal indicating whether the supplied signals are valid. This arrangement supports a one pass test, which reduces production costs and testing duration.

Abstract: A transmitter within a line driver circuit is configured to supply data signals in compliance with the Multilevel Transmission-3 (MLT-3) protocol for high speed data communication. The transmitter comprises a pre-driver system and a final driver. The pre-driver system comprises a plurality of individual pre-drivers that are in parallel. A zero drive logic designates any number of individual pre-drivers as zero drive types, such that these designated zero drive pre-drivers are turned ON during a zero signaling state. The partially turned ON pre-driver system, during the zero state, permits the final driver to rapidly output positive and negative signals in accord with the MLT-3 protocol.

Abstract: A repeater set provides for delaying a character of data that passes through the repeater set from one receive channel to a set of transmit channels. In providing for the delay of a character, the repeater set includes a delay calculator for calculating a character delay value. The repeater set then receives a character that is to be provided on a transmit channel and delays the character in a delay module for a period of time equal to the character delay value. The character delay value is determined by the delay calculator by first calculating a bit delay value and then converting the bit delay value into the character delay value.

Abstract: An optimum equalizer setting is determined for a signal equalizer in a network receiver by successively setting the equalizer to different predetermined settings, detecting timing correlation results between the equalized signal and a recovered clock in a digital phase locked loop, and determining a normalized distribution result for each of the predetermined equalizer settings based on the timing correlation results. The equalizer setting having the minimum normalized distribution result can then be selected as the optimum equalizer setting. Use of the correlation result from the phase locked loop enables the equalizer controller determining the optimum equalizer setting to determine the setting using a closed-loop setting. Hence, the equalizer controller can effectively determine the equalizer setting that causes the minimum amount of jitter in the phase locked loop.

Abstract: A logical repeater set provides for delaying a character of data that passes through the logical repeater set from a receive channel in a receiving repeater set to a set of transmit channels in transmitting repeater sets. In providing for the delay of a character, the receiving repeater set calculates a receive channel character delay value, and receives a character that is to be provided on a transmit channel. The receiving repeater set then delays the character for a period of time equal to the receive channel character delay value and providing the character to the transmitting repeater set. Each transmitting repeater set further calculates a set of transmit channel character delay values for a set of transceivers. Each transmitting repeater set receives a character from the receiving repeater set that is to be provided on a transmit channel and further delays the character by a transmit channel character delay value.

Abstract: A method and system for providing statistical network information carried in a data packet being transmitted on a network. The method includes the steps of receiving a data packet having a data portion on a repeater and transferring the data portion to a management unit. The method further includes the step of appending statistical information to the data portion during an inter-packet gap period. The apparatus for increasing information in a data packet on a network includes a repeater mechanism, a management unit mechanism, and a packet tagging circuit. The repeater mechanism receives a data packet having a data portion, the management unit mechanism determines statistical information based on the data packet, and the packet tagging circuit appends information to the data portion of the data packet during an inter-packet gap period.

Abstract: A reversible media independent interface (MII) circuit is disclosed. The MII circuit comprises a first management circuit and a second management circuit. The first management circuit is operating in a first mode, the first mode being an interface between the MII and a media access control (AC) device. The second management circuit is operating in a second mode, the second mode being an interface between the MII and a physical layer (PHY) device. The MII circuit also includes a plurality of signals being provided to and sent from the MII circuit. A first portion of the plurality of signals are operable within either a physical layer device in a first mode or a media access control device in a second mode. A second portion of the plurality of the signals are provided the first management circuit and the second management circuit.

Abstract: An apparatus and method for shortening propagation delays of a plurality of repeater circuits that are interconnected to form a single repeater. A tree structure that organizes the plurality of repeater circuit so that an activity signal from one repeater circuit is propagated to other repeater circuits via a multi-branching network wherein a downstream repeater circuit is connected to at least two upstream repeater circuits. Any particular repeater circuit notifies the other repeater circuits, via an expansion bus, of a collision whenever two or more upstream indicator signals are asserted, or when at least one upstream indicator signal is asserted and the particular repeater circuit has one port active, or when the particular repeater circuit has multiple ports active. Each repeater circuit asserts an indicator signal to a downstream repeater circuit whenever one of its upstream indicator signals are active or one of its ports is active.

Abstract: In a repeater having multiple ports and receiving at a source port a data packet containing a received address, an address mapping system including a content addressable memory (CAM) with address registers containing stored addresses, and an address mapping matrix coupled to said CAM, for perfectly mapping any of the address registers to any of the ports. According to one aspect of the invention, it operates in a repeater having an address compare and disrupt security system.

Abstract: A method and apparatus for securing a network from access by unauthorized end stations. A port in a multiport repeater can be disabled automatically upon detection of an unknown source address in a data packet. In addition, an interrupt signal is provided to the indicate the detection of an intruder. Further, the disabling of the port can be done substantially immediately to interrupt the re-transmission of a single packet. Alternatively, the disabling of a port can be done programmably after a predetermined number of intruder packets have been detected, or after the verification of packet integrity.

Abstract: A secure repeater implementing data packet masking includes a programmable and selective, on a per port basis, delay disrupt response. A delay disrupt controller receives signals indicating retransmissions of fields from a data packet. These signals include a destination address field and a source address field. A plurality of memories, one associated with each port, determines the associated port's delay response to the data packet. Each memory stores a delay disrupt control code. When the delay disrupt control code for a particular port has a value indicating that the associated port is enabled to delay disruption of a data packet, security marking is disabled until the source address field is retransmitted from the particular port.

Abstract: A system is provided for use in a network to provide authentication of packets of data, provide security to ensure the prevention of unauthorized receipt of data, to provide improved monitoring of the packets of data transmitted and received over such a network, and to detect changes in the network topology. Repeaters utilized in the network are provided with the capability to detect and interpret packet data and the source address (SA) and destination address (DA) fields to provide the improved features.

Abstract: A secure repeater implementing data packet masking includes a programmable and selective, on a per port basis, disrupt response responsive to any of several selectable qualifying conditions. A disrupt controller receives signals indicating various characteristics of fields of a data packet, and other conditions. A register bank includes a plurality of memories, one associated with each port and some of the conditions, assists the disrupt controller to determine the associated port's disrupt response to the data packet. Each memory stores a disrupt control code. When the disrupt control code for a particular port has a value indicating that the associated port is enabled, deassertion of a condition signal associated with that control code results in disruption of a data packet. A cell array permits simple, efficient scaling and formation of integrated semiconductor structures to implement complex disrupt logic equations.

Abstract: An interface to an indicator array for providing status information from a repeater used in a computer network. The interface multiplexes status value signals from the repeater provided to a group of enabled source buffers driving columns of the array. Rows of the array are driven by status enable signals from a sink buffer attached to each row. LEDs of the array have an anode connected to a source buffer and a cathode connected to a sink buffer. Cycling through the source buffer groups and status enable signals provides a 10% duty cycle for each indicator. When status values change more frequently than about once per millisecond, a pulse stretcher is used to extend the perceived duration of the status indication.

Abstract: A method and apparatus for efficiently transferring a data packet on a network. The efficient transfer of data includes compressing the data as the data packet is transmitted from a repeater to a management unit by determining if a destination address of a received packet matches a stored management unit address. When the stored address does not match the destination address, the data packet is compressed. The apparatus includes a repeater, a management unit, and a packet compression mechanism. The apparatus further includes comparator circuit means for determining address comparisons and count comparisons to control data compression.