Patents by Inventor William Loh
William Loh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11050214Abstract: In an ultrastable laser, using a large mode-volume optical resonator, which suppresses the resonator's fast thermal fluctuations, together with the stimulated Brillouin scattering (SBS) optical nonlinearity presents a powerful combination that enables the ability to lase with an ultra-narrow linewidth of 20 Hz. The laser's long-term temperature drift is compensated by using the narrow Brillouin line to sense minute changes in the resonator's temperature (e.g., changes of 85 nK). The precision of this temperature measurement enables the stabilization of resonators against environmental perturbations.Type: GrantFiled: May 2, 2019Date of Patent: June 29, 2021Assignee: Massachusetts Institute of TechnologyInventors: William Loh, Paul William Juodawlkis, Siva Yegnanarayanan
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Patent number: 10502769Abstract: A digital voltmeter, where a number of clock pulses for a first ramp voltage to reach an input voltage is determined. Next, a number of clock pulses for a second ramp voltage to reach the input voltage is determined. One of the first and the second ramp voltages having a least number of clock pulses to reach the input voltage is determined. A determination is made for a number of clock pulses for the determined one of the first and the second ramp voltages to reach a reference voltage. A digital code is generated for the input voltage based on the determined number of clock pulses for reaching the reference voltage and the determined least number of clock pulses for reaching the input voltage.Type: GrantFiled: September 7, 2017Date of Patent: December 10, 2019Inventors: William Loh, Venkata N. S. N. Rao, Prasad Chalasani
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Publication number: 20190341739Abstract: Ultrastable lasers serve as the backbone for advanced scientific experiments and enable atomic spectroscopy and laser interferometry at high levels of precision. But is not clear how to realize an ultrastable laser that is compact and portable for field use. An ultrastable laser source should be insensitive to both short- and long-term fluctuations in temperature, which ultimately broaden the laser linewidth and cause drift in the laser's center frequency. Fortunately, using a large mode-volume optical resonator, which suppresses the resonator's fast thermal fluctuations, together with the stimulated Brillouin scattering (SBS) optical nonlinearity presents a powerful combination that enables the ability to lase with an ultra-narrow linewidth of 20 Hz. The laser's long-term temperature drift is compensated by using the narrow Brillouin line to sense minute changes in the resonator's temperature (e.g., changes of 85 nK).Type: ApplicationFiled: May 2, 2019Publication date: November 7, 2019Applicant: Massachusetts Institute of TechnologyInventors: WILLIAM LOH, Paul William JUODAWLKIS, Siva YEGNANARAYANAN
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Publication number: 20190072589Abstract: A digital voltmeter, where a number of clock pulses for a first ramp voltage to reach an input voltage is determined. Next, a number of clock pulses for a second ramp voltage to reach the input voltage is determined. One of the first and the second ramp voltages having a least number of clock pulses to reach the input voltage is determined. A determination is made for a number of clock pulses for the determined one of the first and the second ramp voltages to reach a reference voltage. A digital code is generated for the input voltage based on the determined number of clock pulses for reaching the reference voltage and the determined least number of clock pulses for reaching the input voltage.Type: ApplicationFiled: September 7, 2017Publication date: March 7, 2019Inventors: William Loh, Venkata N.S.N. Rao, Prasad Chalasani
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Patent number: 9971226Abstract: An optoelectronic filter having at least one input and an output includes a modulator circuit having at least first and second inputs with a first one of the modulator circuit inputs adapted to couple to a respective one of the at least one input of the optoelectronic filter. The modulator circuit receives at least a first radio frequency (RF) signal having a first power level and a second RF signal having a second, different power level at the first one of the modulator circuit inputs and in response thereto generates a modulated signal at an output thereof. The first RF signal is suppressed relative to the second RF signal in the modulated signal. The optoelectronic filter additionally includes a light source adapted to couple to a second one of the modulator circuit inputs. A corresponding method is also provided.Type: GrantFiled: July 31, 2014Date of Patent: May 15, 2018Assignee: Massachusetts Institute of TechnologyInventors: Paul W. Juodawlkis, William Loh, Rajeev J Ram, Siva Yegnanarayanan
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Publication number: 20160170285Abstract: An optoelectronic filter having at least one input and an output includes a modulator circuit having at least first and second inputs with a first one of the modulator circuit inputs adapted to couple to a respective one of the at least one input of the optoelectronic filter. The modulator circuit receives at least a first radio frequency (RF) signal having a first power level and a second RF signal having a second, different power level at the first one of the modulator circuit inputs and in response thereto generates a modulated signal at an output thereof. The first RF signal is suppressed relative to the second RF signal in the modulated signal. The optoelectronic filter additionally includes a light source adapted to couple to a second one of the modulator circuit inputs. A corresponding method is also provided.Type: ApplicationFiled: July 31, 2014Publication date: June 16, 2016Inventors: Paul W. Juodawlkis, William Loh, Rajeev J Ram, Siva Yegnanarayanan
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Patent number: 9292644Abstract: A system and method of designing the physical layout of an SoC incorporating row-based placement of analog standard cells whose heights are constrained to a predetermined row height or integer multiple thereof. A library of analog standard cells may be utilized by an ECAD tool to map, place, and route analog and mixed signal circuits in a manner similar to how such ECAD tool may utilize a library of digital standard cells to map, place, and route digital circuits. Mapping, placing, and routing of digital, analog, and mixed signal circuits may proceed within a unified ECAD SoC physical design flow. Finally, a general type analog standard cell is taught to further increase the speed and efficiency of analog and mixed-signal SoC layout.Type: GrantFiled: August 13, 2012Date of Patent: March 22, 2016Inventors: William Loh, Erik Vaclav Chmelar
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Patent number: 9239896Abstract: A design methodology which prevents functional failure caused by CDM ESD events. A transistor model is used to model the final states of cells, and a simulator is then used to identify invulnerable cells. Cells that are potential failure sites are then identified. The cells which have been identified as being potential victims are replaced by the previously-identified invulnerable cells that have the identical logic function. On the other hand, if a cell with identical function cannot be found, an invulnerable buffer cell (that will not effect logic function) can be inserted in front of the potential victim transistor as protection. By replacing all the potential victim cells with cells which have been determined to be invulnerable, the resulting design will be guaranteed to be CDM ESD tolerant.Type: GrantFiled: October 21, 2008Date of Patent: January 19, 2016Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.Inventors: Choshu Ito, Tze Wee Chen, William Loh
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Patent number: 9087157Abstract: A time division multiplexing intra-chip communication system comprising at least one communication link. Such communication link comprises serialization and transmission circuitry, reception and deserialization circuitry, and at least one coaxial or wafer-level package transmission line interconnect therebetween. Such coaxial or wafer-level package transmission line interconnect may carry signals from such transmit circuitry to such receive circuitry. Such intra-chip communication links may achieve single-cycle operation or multi-cycle operation. Single single-cycle operation may be conducive to synchronous FSM design methodologies while multi-cycle operation may be conducive to data transfers to and from memory.Type: GrantFiled: February 26, 2012Date of Patent: July 21, 2015Inventors: William Loh, Erik Vaclav Chmelar
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Patent number: 8798981Abstract: A method for simulating a response of a circuit to an ESD input stimulus applied to the circuit includes the steps of: receiving a description of the circuit into a circuit simulation program, the circuit including at least one mutual inductance element indicative of magnetic coupling in the circuit; generating a linear approximation of nonlinear elements in the circuit at respective DC bias points of the nonlinear elements; obtaining a frequency domain transfer function of the circuit; obtaining a time domain impulse response of the circuit as a function of the frequency domain transfer function; integrating the time domain impulse response to yield a step response of the circuit, the step response being indicative of a response of the circuit to the ESD input stimulus; and analyzing the step response of the circuit to determine whether the circuit will operate within prescribed parameters corresponding to the circuit.Type: GrantFiled: June 23, 2008Date of Patent: August 5, 2014Assignee: LSI CorporationInventors: Choshu Ito, William Loh
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Publication number: 20130042216Abstract: A system and method of designing the physical layout of an SoC incorporating row-based placement of analog standard cells whose heights are constrained to a predetermined row height or integer multiple thereof. A library of analog standard cells may be utilized by an ECAD tool to map, place, and route analog and mixed signal circuits in a manner similar to how such ECAD tool may utilize a library of digital standard cells to map, place, and route digital circuits. Mapping, placing, and routing of digital, analog, and mixed signal circuits may proceed within a unified ECAD SoC physical design flow. Finally, a general type analog standard cell is taught to further increase the speed and efficiency of analog and mixed-signal SoC layout.Type: ApplicationFiled: August 13, 2012Publication date: February 14, 2013Inventors: William Loh, Erik Vaclav Chmelar
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Publication number: 20120224613Abstract: A time division multiplexing intra-chip communication system comprising at least one communication link. Such communication link comprises serialization and transmission circuitry, reception and deserialization circuitry, and at least one coaxial or wafer-level package transmission line interconnect therebetween. Such coaxial or wafer-level package transmission line interconnect may carry signals from such transmit circuitry to such receive circuitry. Such intra-chip communication links may achieve single-cycle operation or multi-cycle operation. Single single-cycle operation may be conducive to synchronous FSM design methodologies while multi-cycle operation may be conducive to data transfers to and from memory.Type: ApplicationFiled: February 26, 2012Publication date: September 6, 2012Inventor: William Loh
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Patent number: 8121186Abstract: Various embodiments of the present invention provide systems and methods for signal equalization, and in some cases analog to digital conversion. For example, an analog to digital converter is disclosed that includes a comparator bank that receives a reference indicator and is operable to provide a decision output based at least in part on a comparison of an analog input with a reference threshold corresponding to the reference indicator. A range selection filter is included that has a first adjustment calculation circuit and a second adjustment calculation circuit. The first adjustment calculation circuit is operable to calculate a first adjustment feedback value based at least in part on a speculation that the decision output is a first logic level, and the second adjustment calculation circuit is operable to calculate a second adjustment feedback value based at least in part on a speculation that the decision output is a second logic level.Type: GrantFiled: June 6, 2008Date of Patent: February 21, 2012Assignee: LSI CorporationInventors: Erik Chmelar, Choshu Ito, William Loh
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Publication number: 20120028863Abstract: The present invention is generally directed to methods of making application-specific finished lubricant compositions comprising bio-derived diester species. In some embodiments, bio-derived fatty acid moieties are reacted with Fischer-Tropsch/gas-to-liquids reaction products and/or by-products (e.g., gas-to-liquids-produced ?-olefins) to yield bio-derived diester species that can then be selectively blended with base oil and one or more additive species to yield an application-specific finished lubricant product having a biomass-derived component.Type: ApplicationFiled: July 29, 2010Publication date: February 2, 2012Inventors: David Christian Kramer, Nicole A. Ketterer, Nathan Todd Knotts, Mark Edward Okazaki, Stephen Joseph Miller, Saleh A. Elomari, Ravindra Shah, Allan George Hee, William Loh, Zhen Zhou, Randolph Albert Baer, John A. Zakarian, Gian Lawrence Fagan, Samil Beret
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Patent number: 8093188Abstract: An ashless lubricating oil, comprising a base oil having a viscosity index greater than 150, wherein the base oil is made from a blend of petroleum-based wax and Fischer-Tropsch derived wax.Type: GrantFiled: December 23, 2009Date of Patent: January 10, 2012Assignee: Chevron U.S.A. Inc.Inventors: William Loh, John M. Rosenbaum, Nancy J. Bertrand, Patricia LeMay, Mark E. Okazaki
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Patent number: 7973692Abstract: Various embodiments of the present invention provide systems and methods for analog to digital conversion. For example, a latch based analog to digital converter is disclosed that includes a first interleave with a set of comparators, a selector circuit and a latch. The set of comparators is operable to compare an analog input with respective reference voltages, and is synchronized to a clock phase. The selector circuit is operable to select an output of one of the set of comparators based at least in part on a selector input. A first interleave output is derived from the selected output. The latch receives a second interleave output from a second interleave and is transparent when the clock phase is asserted. The selector input includes an output of the latch.Type: GrantFiled: June 6, 2008Date of Patent: July 5, 2011Assignee: LSI CorporationInventors: Erik Chmelar, Choshu Ito, William Loh
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Patent number: 7956790Abstract: Various embodiments of the present invention provide systems and methods for analog to digital conversion. For example, a retimed analog to digital converter is disclosed that includes a first set of sub-level interleaves and a second set of sub-level interleaves. The first set of sub-level interleaves includes a first sub-level interleave with a first set of comparators synchronized to a first clock phase, and a second sub-level interleave with a second set of comparators synchronized to a second clock phase. The second set of sub-level interleaves includes a third sub-level interleave with a third set of comparators synchronized to a third clock phase, and a fourth sub-level interleave with a fourth set of comparators synchronized to a fourth clock phase.Type: GrantFiled: June 6, 2008Date of Patent: June 7, 2011Assignee: LSI CorporationInventors: Erik Chmelar, Choshu Ito, William Loh
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Patent number: 7944655Abstract: An ESD protection circuit for protecting a host circuit coupled to a signal pad from an ESD event occurring at the signal pad includes at least one MEMS switch which is electrically connected to the signal pad. The MEMS switch includes a first contact structure adapted for connection to the signal pad, and a second contact structure adapted for connection to a voltage supply source. The first and second contact structures are coupled together during the ESD event for shunting an ESD current from the signal pad to the voltage supply source. The first and second contact structures are electrically isolated from one another in the absence of the ESD event. At least one of the first and second contact structures includes a passivation layer for reducing contact adhesion between the first and second contact structures.Type: GrantFiled: May 28, 2008Date of Patent: May 17, 2011Assignee: LSI CorporationInventors: Tze Wee Chen, William Loh, Choshu Ito
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Publication number: 20100195776Abstract: Various embodiments of the present invention provide systems and methods for analog to digital conversion. For example, a latch based analog to digital converter is disclosed that includes a first interleave with a set of comparators, a selector circuit and a latch. The set of comparators is operable to compare an analog input with respective reference voltages, and is synchronized to a clock phase. The selector circuit is operable to select an output of one of the set of comparators based at least in part on a selector input. A first interleave output is derived from the selected output. The latch receives a second interleave output from a second interleave and is transparent when the clock phase is asserted. The selector input includes an output of the latch.Type: ApplicationFiled: June 6, 2008Publication date: August 5, 2010Inventors: Erik Chmelar, Choshu Ito, William Loh
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Publication number: 20100194616Abstract: Various embodiments of the present invention provide systems and methods for analog to digital conversion. For example, a retimed analog to digital converter is disclosed that includes a first set of sub-level interleaves and a second set of sub-level interleaves. The first set of sub-level interleaves includes a first sub-level interleave with a first set of comparators synchronized to a first clock phase, and a second sub-level interleave with a second set of comparators synchronized to a second clock phase. The second set of sub-level interleaves includes a third sub-level interleave with a third set of comparators synchronized to a third clock phase, and a fourth sub-level interleave with a fourth set of comparators synchronized to a fourth clock phase.Type: ApplicationFiled: June 6, 2008Publication date: August 5, 2010Inventors: Erik Chmelar, Choshu Ito, William Loh