Abstract: A lubricating oil (made from Group III base oil having a sequential number of carbon atoms) having a VI between 155 and 300, a RPVOT greater than 680 minutes, and a kinematic viscosity at 40° C. from 19.8 cSt to 748 cSt. A lubricating oil having a high VI and high RPVOT comprising: a) a Group III base oil with a sequential number of carbon atoms, and defined cycloparaffin composition or low traction coefficient, b) an antioxidant additive concentrate and c) no VI improver. A process comprising: a) hydroisomerization dewaxing of a waxy feed, b) fractionating the produced base oil, c) selecting a fraction having a VI greater than 150, and a high level of molecules with cycloparaffinic functionality or a low traction coefficient, and d) blending the fraction with an antioxidant additive concentrate. Also, a method of improving the oxidation stability of a lubricating oil.

Abstract: An improvement to a digital integrated circuit of the type having a functional circuit that is susceptible to damage from an electrostatic discharge. An electrostatic discharge protection element is placed in series with the functional circuit and disposed upstream in a normal direction of current flow from the functional circuit. The electrostatic discharge protection element includes at least one of a resistive choke that exhibits thermal runaway and an inductive choke.

Abstract: Embodiments of the invention include a semiconductor integrated circuit package that includes a substrate having an integrated circuit die attached thereto. The package includes a ESD shield attached to the substrate. The ESD shield configured to increase the ESD hardness of the package. The ESD shield can further serve to stiffen the package to prevent warping and operate as a heat spreader.

Abstract: An electrostatic discharge protection circuit adapted to reduce an electrostatic discharge event on a line of an integrated circuit. The protection circuit includes an NMOS transistor having a source contact that is electrically connected to the line. A drain contact is electrically connected to a logical low voltage, and a gate contact is also electrically connected to the logical low voltage, through a resistor. A substrate bias pump is electrically connected to a back gate of the NMOS transistor, where the bias pump provides a steady state direct current negative bias during normal operation of the integrated circuit when there is no electrostatic discharge event.

Abstract: A system and method for protecting a circuit. The system includes a protection circuit that includes an inverter and a capacitor coupled to the inverter. The inverter and the capacitor are implemented using logic circuits of a circuit core, and the inverter shunts electrostatic discharge ESD current through the capacitor. According to the system and method disclosed herein, because the protection circuit shunt circuit shunts ESD current using logic circuits of the circuit core, ESD protection is achieved while not requiring large FETs. Also, the protection circuit protects circuits against ESD events that conventional FET cannot protect.

Abstract: The present invention provides a system and method for electrostatic discharge (ESD) testing. The system includes a circuit that has a switch coupled to an input/output (I/O) circuit of a device under test (DUT), a charge source coupled to the switch, and a control circuit coupled to the switch, wherein the control circuit turns on the switch to discharge an ESD current from the charge source to the I/O circuit, and wherein the circuit is integrated into the DUT. According to the system and method disclosed herein, the system provides on-chip ESD testing of a DUT without requiring expensive and specialized test equipment.

Abstract: Methods and structure for improved design remediation for previously inexplicable damage to core circuits of an application circuit design caused by CDM ESD events. Features and aspects hereof note that such previously inexplicable damage to core circuits of an application circuit design is caused by inductive coupling between the non-core circuits and the core circuits of an application circuit design. Features and aspects hereof automatically alter an application circuit design to provide remediation by various techniques to reduce the magnitude of such inductive coupling and to thereby reduce susceptibility of the application circuit to damage from CDM ESD events. The modifications may be enforced as rules during initial design of the application circuit or as reconfiguration of a design in response to simulation to discover inappropriate coupling in the design.

Abstract: Methods and structure for improved simulation of CDM ESD events and for remediation of circuit designs correcting for previously inexplicable damage to core circuits of an application circuit design caused by such events. Features and aspects hereof note that such previously inexplicable damage to core circuits of an application circuit design is caused by inductive coupling between the non-core circuits and the core circuits of an application circuit design. Improved simulation techniques in accordance with features and aspects hereof may predict where such inductive coupling may cause damage to core circuits. Other features and aspects hereof may alter an application circuit design to provide remediation by automated insertion of additional buffer circuitry to core traces of the core circuitry that may be impacted by such inductive coupling.

Abstract: A clock distribution network for an integrated circuit includes a clock driver for generating a clock signal having a selected clock frequency, a clock net coupled to the clock driver wherein the clock net has a capacitive reactance, and an inductor coupled to the clock net wherein the inductor has an inductive reactance that is substantially equal to the capacitive reactance of the clock net at the selected clock frequency to minimize clock driver output current.

Abstract: A method for calculating frequency-dependent impedance in an integrated circuit (IC) having transistors coupled together by a line follows. First, partition the line into a plurality of rectangles of constant material. Then, solve for the minimum dissipated power in the plurality of rectangles. Finally, determine the frequency-dependent impedance from the minimum dissipated power.

Abstract: A bed comprises a mattress supported on a support surface. The mattress has first and second inflatable cells for supporting a patient.

Abstract: The present invention is directed to a field programmable platform array (FPPA). In an exemplary aspect of the present invention, a method for providing field programmable platform array units (PAUs) may include the following steps. First, N by M array of platform array units may be cut from a field programmable platform array wafer according to a customer's order, where N and M are positive integers. The field programmable platform array wafer is a wafer with all silicon layers and metal layers already built and includes a plurality of platform array units. The platform array units may be field programmable by a customer, and each platform array unit may include at least one core and at least one processor. Interconnect between any two of the platform array units may be pre-routed on chip. Next, the N by M array of platform array units may be packaged and tested.

Abstract: A clock distribution network for an integrated circuit includes a clock driver for generating a clock signal having a selected clock frequency, a clock net coupled to the clock driver wherein the clock net has a capacitive reactance, and an inductor coupled to the clock net wherein the inductor has an inductive reactance that is substantially equal to the capacitive reactance of the clock net at the selected clock frequency to minimize clock driver output current.

Abstract: A bed comprises a mattress supported on a support surface. The mattress has first and second inflatable cells for supporting a patient.

Abstract: A bed comprises a mattress supported on a support surface. The mattress has first and second inflatable cells for supporting a patient.

Abstract: A bed comprises a mattress supported on a support surface. The mattress has first and second inflatable cells for supporting a patient.

Abstract: A bed configured to support a patient having a weight comprises a frame, a patient support, and a plurality of sensors coupled between the frame and the patient support. Each of the plurality of sensors is configured to generate an analog signal in response to a portion of the weight of the patient on the patient support. The bed also comprises a circuit coupled to the plurality of sensors to receive the analog signals therefrom. The circuit includes a plurality of analog-to-digital converters, each analog-to-digital converter being coupled to one of the sensors to generate a separate digital signal for each of the plurality of sensors, and a processor coupled to the plurality of analog-to-digital converters to determine the weight of the patient on the patient support.

Abstract: A bed configured to support a patient having a weight comprises a frame, a patient support, and a plurality of sensors coupled between the frame and the patient support. Each of the plurality of sensors is configured to generate an analog signal in response to a portion of the weight of the patient on the patient support. The bed also comprises a circuit coupled to the plurality of sensors to receive the analog signals therefrom. The circuit includes a plurality of analog-to-digital converters, each analog-to-digital converter being coupled to one of the sensors to generate a separate digital signal for each of the plurality of sensors, and a processor coupled to the plurality of analog-to-digital converters to determine the weight of the patient on the patient support.

Abstract: A bed for supporting a patient having a seat panel and a back panel coupled together by a joint assembly that allows the panels to rotate about an axis coincident with the patient's hip joint.

Abstract: A patient care bed with a patient weighing system having a first frame having a series of support units attached at designated locations and a second frame supported by the support units. The support units each having a load cell which senses a part of the weight supported by a second frame.