Abstract: We disclose methods, apparatus, and systems for improving semiconductor device yield and/or reliability through bias temperature instability (BTI). One device may comprise a plurality of cells of an array, wherein each of the cells comprises a pass gate and a latch; a plurality of word lines, wherein each word line controls access to each pass gate of a first number of cells; a word line driver electrically connected to each word line; a row decoder configured to authorize or deauthorize a write voltage to each word line through the word line driver, wherein the write voltage is selected from an operational write voltage or a first write voltage; and a control line configured to provide an operational write voltage or a first write voltage to each word line authorized by the row decoder, wherein the first write voltage is greater than an operational write voltage.

Abstract: A method and an apparatus for identifying non-intrinsic defect bits from a population of failing bits for failure analysis to characterize the extrinsic failure mechanisms is provided. Embodiments include performing a failure mode test on a bank of a memory array at different low VDD; determining optimal bank size to observe plateaus of fail counts; determining fail counts of the bank at each different low VDD; determining a plateau of the fail counts; determining whether the plateau represents extrinsic bits of the bank; and submitting the extrinsic bits for root cause analysis.

Abstract: There is set forth herein a semiconductor structure including a plurality of test devices, the plurality of test devices including a first test device and a second test device. A semiconductor structure can also include a waveform generating circuit, the waveform generating circuit configured for application of a first stress signal waveform having a first duty cycle to the first test device, and a second stress signal waveform having a second duty cycle to the second test device. A semiconductor structure can include a selection circuit associated with each of the first test device and the second test device for switching between a stress cycle and a sensing cycle.

Abstract: A method and an apparatus for identifying non-intrinsic defect bits from a population of failing bits for failure analysis to characterize the extrinsic failure mechanisms is provided. Embodiments include performing a failure mode test on a bank of a memory array at different low VDD; determining optimal bank size to observe plateaus of fail counts; determining fail counts of the bank at each different low VDD; determining a plateau of the fail counts; determining whether the plateau represents extrinsic bits of the bank; and submitting the extrinsic bits for root cause analysis.

Abstract: Wafer test structures and methods of providing wafer test structures are described. The methods include: fabricating multiple test devices and multiple fuse devices on the wafer, each test device having a respective fuse device associated therewith, which open circuits upon failure of the test device; and fabricating a selection circuit operative to selectively connect one test device to a sense contact pad, and the other test devices to a stress contact pad. The selection circuit facilitates sensing one or more electrical signals of the one test device by electrical contact with the sense contact pad, while stress testing the other test devices by electrical contact with the stress contact pad. In one embodiment, each test device has respective first and second switch devices, operative to selectively electrically connect the test device to the sense or stress contact pads. In another embodiment, the method includes wafer testing using the test structure.

Abstract: At least one method and system disclosed herein involves testing of integrated circuits. A device having at least one transistor and at least one dielectric layer is provided. A first voltage is provided during a first time period for performing a stress test upon the device. A second voltage is provided during a second time period for discharging at least a portion of the charge built-up as a result of the first voltage. The second voltage is of an opposite polarity of the first voltage. A sense function is provided during a third time period for determining a result of the stress test. Data relating to a breakdown of the dielectric layer based upon the result of the stress test is acquired, stored and/or transmitted.

Abstract: There is set forth herein a semiconductor structure including a plurality of test devices, the plurality of test devices including a first test device and a second test device. A semiconductor structure can also include a waveform generating circuit, the waveform generating circuit configured for application of a first stress signal waveform having a first duty cycle to the first test device, and a second stress signal waveform having a second duty cycle to the second test device. A semiconductor structure can include a selection circuit associated with each of the first test device and the second test device for switching between a stress cycle and a sensing cycle.

Abstract: Wafer test structures and methods of providing wafer test structures are described. The methods include: fabricating multiple test devices and multiple fuse devices on the wafer, each test device having a respective fuse device associated therewith, which open circuits upon failure of the test device; and fabricating a selection circuit operative to selectively connect one test device to a sense contact pad, and the other test devices to a stress contact pad. The selection circuit facilitates sensing one or more electrical signals of the one test device by electrical contact with the sense contact pad, while stress testing the other test devices by electrical contact with the stress contact pad. In one embodiment, each test device has respective first and second switch devices, operative to selectively electrically connect the test device to the sense or stress contact pads. In another embodiment, the method includes wafer testing using the test structure.

Abstract: A methodology for inline characterization and temperature profiling that enables parallel measurement of device characteristics at multiple temperatures and the resulting device are disclosed. Embodiments may include calibrating a first device under test (DUT) with respect to at least one heating structure in a metal layer of an integrated circuit (IC), applying a heater voltage to the at least one heating structure, and measuring at least one characteristic of the first DUT at a first temperature corresponding to the heater voltage.

Abstract: At least one method and system disclosed herein involves performing a time-dependent dielectric breakdown (TDDB) test and a bias temperature instability (BTI) test on a device. A device having at least one transistor and at least one dielectric layer is provided. A test signal is provided for performing a TDDB test and a BTI test on the device. The TDDB test and the BTI test are performed substantially simultaneously on the device based upon the test signal. The data relating to a breakdown of the dielectric layer and at least one characteristic of the transistor based upon the TDDB test and the BTI test is acquired, stored, and/or transmitted.

Abstract: The present disclosure relates to the identification of a subject that is affected with, or predisposed to, autism or to one or more autism spectrum disorders (ASD). The present disclosure includes methods related to the association of certain genetic markers with autism and/or ASD. More particularly, the present disclosure is related to methods and diagnostic tests for diagnosing or predicting ASD in an individual.

Abstract: An integrated circuit device includes at least one test device and a stress generator coupled to the test device and operable to cycle the at least one test device to generate an AC stress. A method for testing an integrated circuit device including at least one test device and a stress generator coupled to the test device includes enabling the stress generator to cycle the at least one test device to generate an AC stress and measuring at least one parameter of the test device to determine an effect of the AC stress.

Abstract: Methods are provided for operating a memory device. An exemplary method involves obtaining a standby current through a memory block and adjusting a supply voltage for the memory block based on the obtained standby current. An exemplary memory device includes a block of one or more memory cells, a voltage regulating element coupled to the block to provide a supply voltage to the block, a current sensing element coupled to the block to measure current through the block, and a control module coupled to the voltage regulating element and the current sensing element to adjust the supply voltage provided by the voltage regulating element based on a measured current through the block obtained from the current sensing element.

Abstract: Embodiments of the methods and apparatus for automatic cross language program code translation are provided. One or more characters of a source programming language code are tokenized to generate a list of tokens. Thereafter, the list of tokens is parsed to generate a grammatical data structure comprising one or more data nodes. The grammatical data structure may be an abstract syntax tree. The one or more data nodes of the grammatical data structure are processed to generate a document object model comprising one or more portable data nodes. Subsequently, the one or more portable data nodes in the document object model are analyzed to generate one or more characters of a target programming language code.

Abstract: Embodiments of the invention may provide methods and/or systems for converting a source application to a platform-independent application. Source programming language code of the source application may be translated to target programming language code of the platform-independent application. The source programming language code may comprise Connected Limited Device Configuration (CLDC) code, and the platform-independent programming language may be independent of one or more device platforms. Further, one or more source resources associated with the source application may be converted to one or more target resources.

Abstract: Embodiments of the invention provide a platform-independent application development framework for programming an application. The framework comprises a content interface configured to provide an Application Programming Interface (API) to program the application comprising a programming code to be executed on one or more platforms. The API provided by the framework is independent of the one or more platforms. The framework further comprises an application environment configured to provide an infrastructure that is independent of the one or more platforms and one or more plug-in interfaces configured to provide an interface between the application environment and the one or more platforms.

Abstract: Managing assets during translation of source application to a target application may involve analyzing the source application to generate a database of characteristics of source assets. Thereafter, performance metrics for a target platform may be determined based on the characteristics of the source assets. Subsequently, the source assets may be processed based on the performance metrics to generate target assets.

Abstract: An integrated circuit device includes at least one test device and a stress generator coupled to the test device and operable to cycle the at least one test device to generate an AC stress. A method for testing an integrated circuit device including at least one test device and a stress generator coupled to the test device includes enabling the stress generator to cycle the at least one test device to generate an AC stress and measuring at least one parameter of the test device to determine an effect of the AC stress.

Abstract: Methods are provided for operating a memory device. An exemplary method involves obtaining a standby current through a memory block and adjusting a supply voltage for the memory block based on the obtained standby current. An exemplary memory device includes a block of one or more memory cells, a voltage regulating element coupled to the block to provide a supply voltage to the block, a current sensing element coupled to the block to measure current through the block, and a control module coupled to the voltage regulating element and the current sensing element to adjust the supply voltage provided by the voltage regulating element based on a measured current through the block obtained from the current sensing element.

Abstract: In accordance with a exemplary embodiments, methods for performing reliability testing of a plurality of transistors formed on a substrate includes simultaneously stressing the plurality of transistors by applying a voltage potential from each of a plurality of voltage sources to respective drain contacts of a like plurality of row groups and to gate contacts of a like plurality of column groups for a time interval, while applying a reference potential to the substrate and source contacts of the plurality of transistors. After stressing the plurality of transistors for a time interval, the transistors are each measured individually to collect reliability data.