Abstract: A clamp circuit including a clamping capacitor and a differential amplifier charge and discharge the clamping capacitor in accordance with the magnitude of difference signals applied to the differential amplifier's inverting and non-inverting inputs. The inverting input receives the voltage produced by the clamping capacitor. This voltage is digitized by an analog-to-digital converter (ADC) and is set to a reference voltage range by a voltage divider network. The ADC output signal is compared to a given reference level corresponding to a selected voltage in the reference voltage range to produce a difference output signal. This difference output signal is summed with the selected voltage in the reference voltage range and applied to the non-inverting input of the differential amplifier to produce a clamp voltage with substantially minimum offsets due to the amplifier, ADC and DAC.

Abstract: A color palette selects a master clock from plural clock signals received at clock input terminals in response to a master clock selection control word received at control data terminals. A circuit forms a plurality of divided down clock signals from selected divide ratios of the master clock. A circuit selects a shift clock from among the divided down clock signals in response to at least some bits of an output clock selection control word received at the control data terminals. A circuit selectively enables and disables the shift clock in response to blanking data. A circuit selects a video clock from among the divided down clock signals in response to at least some bits of the output clock selection control word. A circuit synchronizes multiple bit words of color code received at color code input terminals with the master clock. A circuit outputs at least one memory recall address in response to receiving each multiple bit word of color code.

Abstract: An integrated circuit buffer includes a source follower output transistor having an output and also connected by a voltage dropping circuit to a supply rail thereby introducing a controlled amount of Miller effect capacitance in the source follower output transistor. The buffer also has a common source output transistor and a unidirectional conducting circuit connecting between the common source output transistor and the source follower output transistor. Other buffers, palette devices, computer graphics systems and methods are also disclosed.

Abstract: A memory cell constructed in accordance with the present invention includes a node operable to present an electrical level representing a first state or a second state. Further included is a first switching device having a first terminal connected to the node such that if the first switching device were to close, the electrical level at the node would be connected to a second terminal of the first switching device. Additionally, second and third switching devices are provided both having first and second terminals and both operable to switch as a function of the state at the node. Finally, a single control switching device is provided in association with the second and third switching devices wherein a control signal switches the control switching device such that the state at the node may be determined by connecting to the first terminals of the second and third switching devices.

Abstract: A method and circuitry are provided for current input analog to digital conversion. A current input (14) is conducted through an input path. The current input is directed through a plurality of current paths (30a-d). A current through each current path (30a-d) is compared against an associated reference current (36a-d), and a respective output signal (34a-d) indicative thereof is output, such that the respective output signals (34a-d) are indicative of a magnitude of the current input (14).

Abstract: A method and apparatus for an improved multiple channel sensor interface circuit is described which comprises a plurality of input integrator circuits (35) coupled in parallel; a switched capacitor multiplexer (37) coupled to the input integrator circuits (35); and an output integrator stage (39) coupled to the switched capacitor multiplexer (37). An additional embodiment is described wherein a multiple channel voltage sensor interface circuit comprising a plurality of switched capacitor storage elements (S26 . . . S28) is coupled to a plurality of inputs; a plurality of integrator amplifiers (51, 53) is coupled to the switched capacitor storage elements (C22 . . . C30); and timing circuitry is coupled to the switched capacitor storage elements (C221 . . . C30) and to integrator amplifiers (51, 53) operable to selectively enable sampling of the inputs.

Abstract: An integrated circuit buffer includes a source follower output transistor having an output and also connected by a voltage dropping circuit to a supply rail thereby introducing a controlled amount of Miller effect capacitance in the source follower output transistor. The buffer also has a common source output transistor and a unidirectional conducting circuit connecting between the common source output transistor and the source follower output transistor. Other buffers, palette devices, computer graphics systems and methods are also disclosed.

Abstract: An integrated circuit buffer includes an input differential amplifier with a first current source transistor and a network with second current source transistors and cascode transistors loading the differential amplifier. Further included is a network having transistors and a resistance connected to introduce bias voltages to the first and second current source transistors to set a common mode level for the cascode transistors wherein the bias voltages are generated by the network independently of said common mode level. The bias voltages establish a respective lesser current from the first current source transistor and a greater current from the second current source transistors connected to the cascode transistors. Other circuits, devices, systems and methods are also disclosed.

Abstract: Capacitance compensation techniques are used to reduce capacitive effects that impact on the performance of current steering circuits (FIG. 1). In an isolation technique (FIGS. 2a-2e), a resistor (R) or a diode (D) is coupled to a data-switched transistor to dampen voltage perturbations associated with the gate-to-source capacitance. In a design variable technique FIGS. 3a-3d), a transistor (PDV) is included in either the output or ground legs of the current steering circuit to provide a design variable to counteract the capacitive effects of the associated data-switched (PDX/NDX) or voltage-controlled (PREF) transistor. In a bipolar substitution technique (FIG. 4), a data-switched bipolar transistor (QDX) is substituted for the data-switched MOS transistor, and made sufficiently small to significantly reduce junction capacitance. In addition, capacitive effects can be reduced by introducing fabrication alterations (FIGS.

Abstract: An amplifier includes an input circuit for alternately selecting input signals to be compared and a first bias circuit for producing self-bias when one of the input signals is selected. A second bias circuit stores the self-bias for use in the amplifier when the other of the input signals is selected for rejecting noise which may accompany power supply voltage applied to the amplifier.

Abstract: A TTL compatible CMOS high-speed lower-power supply-independent input buffer has a first current mirror which supplies current to a reference node of the input buffer when the signal at the input node of the buffer goes to a high state. An MOS transistor has its gate connected to the input node and switches hard on when the input node goes to a high level, pulling the reference node to a low level. A second current mirror is provided which injects current into the reference node for a predetermined period of time after the voltage level at the input of the buffer goes to a low level to pull the reference node to a high level. Both the first and second current mirror are switched on only during transition states of the input buffer, to minimize power dissipation when the input buffer is in its quiescent state.

Abstract: A dual-slope A/D converter circuit has an oscillator (14) whose timing frequency is determined by the value of an oscillator resistor (70) and a oscillator capacitor (72). An integrator (66) integrates an input voltage at a rate determined by an integrating resistor (64) and an integrating capacitor (68). The oscillator resistor (70) and integrator resistor (64) are designed such that their ratio will remain constant despite variations in actual value due to manufacturing inaccuracies. The oscillator capacitor (72) and integrating capacitor (68) are similarly designed. Consequently, an optimum peak integration value can be obtained at full scale input despite variations in actual resistive and capacitive values.

Abstract: A differential amplifier (10) having a circuit (18) which images or simulates the bias current flowing in an input stage (34) of the differential amplifier (10) is disclosed. This image circuit (18) resembles a differential amplifier input stage, couples to the signal inputs (28, 30) of the differential amplifier (10), and provides an output signal that reflects such bias current. One embodiment of the present invention feeds this output signal back to the differential amplifier input stage (34) to improve regulation of a constant current source (26). Another embodiment uses this signal to switch current from an external source (86) to the differential amplifier input stage (34) when a constant current source (26) within the differential amplifier input stage (34) fails to maintain a constant current supply.

Abstract: A dual-slope A/D converter circuit has an oscillator (14) whose timing frequency is determined by the value of an oscillator resistor (70) and a oscillator capacitor (72). An integrator (66) integrates an input voltage at a rate determined by an integrating resistor (64) and an integrating capacitor (68). The oscillator resistor (70) and integrator resistor (64) are designed such that their ratio will remain constant despite variations in actual value due to manufacturing inaccuracies. The oscillator capacitor (72) and integrating capacitor (68) are similarly designed. Consequently, an optimum peak integration value can be obtained at full scale input despite variations in actual resistive and capacitive values.

Abstract: A data latch with substantially zero hold time and with immunity to input data changes occurring after the latch has slewed toward a definable logic state. An input data flip-flop (10) is coupled via transfer transistors (40, 42) to an output data flip-flop (12). Output nodes (36,38) of the output data flip-flop (12) are prechargeable. Inhibit transistors (24,30) are cross-coupled between the input data flip-flop (10) and the output data flip-flop (12) to prevent input data changes from affecting the latch once the output data flip-flop (12) slews toward a definable stable state.

Abstract: Disclosed is a supply voltage monitor for detecting the asymmetric decay of one voltage source (V.sub.dd) with respect to another voltage source (V.sub.ss). The monitor circuit (24) includes a resistive voltage divider (26) having a plurality of voltage tap positions (32,35,38). A sensor transistor (40) monitors the voltage between a common connection (16) connecting the voltage sources and the voltage at a desired tap position (38) of the divider network (26). On detecting an imbalance between the voltage sources (V.sub.dd, V.sub.ss), the sensor transistor (40) drives a current mirror circuit (42). The current mirror circuit (42) defines an output (50) of the monitor circuit (24), together with a reference transistor (48) biased by a voltage of the divider network (26).

Abstract: A fast one way amplifier/comparator stage includes a transconductance square law device (20) for receiving an input voltage and a reference voltage and outputting a current that varies as the square law of the voltage difference. This current is converted to a voltage in a transresistance device (26) for controlling the switch element (30). The switch element (30) is operable to switch a capacitive load to either a positive rail or to a negative rail at a fast slew rate. The amplifier/comparator stage only draws current when the switch element (30) is conducting. When the switch element (30) is nonconducting, a load transistor (38) pulls the load (36) to the opposite terminal from that to which the switch element (30) is connected.

Abstract: A folded cascode amplifier with rail-to-rail common-mode range utilizes a fully differential input with two sets of input common source amplifier devices to allow rail-to-rail common-mode range. The first set of devices utilizes N-channel transistors (28) and (32) to provide operation in one direction and P-channel transistors (38) and (42) to allow operation in the other direction. Two common gate amplifier output legs are provided for generating a differential voltage between an output node (50) and an output node (48) in a cascode configuration. A feedback circuit is provided for maintaining node (50) at analog ground over the full common-mode range of the input voltage. The feedback circuit utilizes a current source with transistors (88) and (90) and a differentially configured set of transistors (80) and (82) to control a feedback transistor (86).