Abstract: The present invention relates generally to protection of integrated circuits from electrostatic discharges and more specifically to the use of devices formed in isolated well regions for electrostatic discharge protection. One aspect of the present invention is an ESD protection circuit that includes a first FET and a second FET. The drain of the first FET is coupled to an ESD susceptible node and the source of the first FET is coupled to a first voltage terminal. The gate and a well of the first FET are coupled together and to the drain of the second FET. The source of the second FET is coupled to the first voltage terminal. The gate of the second FET is coupled to a second voltage terminal. The second voltage terminal is connected to a voltage source that is at the first voltage when the circuit is not powered, and at a voltage above the threshold voltage of the second FET when the circuit is powered. The well in which the first FET is formed is electrically isolated from other wells in the substrate.

Abstract: A method and semiconductor structure that uses a field enhanced region where the oxide thickness is substantially reduced, thereby allowing antifuse programming at burn-in voltages which do not damage the standard CMOS logic. The semiconductor device comprises a substrate that has a raised protrusion terminating at a substantially sharp point, an insulator layer over the raised protrusion sufficiently thin to be breached by a breakdown voltage applied to the sharp point, a region comprised of a material on the insulator over the raised protrusion for becoming electrically coupled to the substrate after the insulator layer is breached by the breakdown voltage, and a contact for supplying the breakdown voltage to the substrate.

Abstract: An anti-fuse structure that can be programmed at low voltage and current and which potentially consumes very little chip spaces and can be formed interstitially between elements spaced by a minimum lithographic feature size is formed on a composite substrate such as a silicon-on-insulator wafer by etching a contact through an insulator to a support semiconductor layer, preferably in combination with formation of a capacitor-like structure reaching to or into the support layer. The anti-fuse may be programmed either by the selected location of conductor formation and/or damaging a dielectric of the capacitor-like structure. An insulating collar is used to surround a portion of either the conductor or the capacitor-like structure to confine damage to the desired location. Heating effects voltage and noise due to programming currents are effectively isolated to the bulk silicon layer, permitting programming during normal operation of the device.

Abstract: Silicon is formed at selected locations on a substrate during fabrication of selected electronic components. A dielectric separation region is formed within the top silicon layer, and filled with a thermally conductive material. A liner material may be optionally deposited prior to depositing the thermally conductive material. In a second embodiment, a horizontal layer of thermally conductive material is also deposited in an oxide layer or bulk silicon layer below the top layer of silicon.

Abstract: A first one time, voltage programmable logic element is provided in a semiconductor substrate of first conductivity type that comprises a first layer beneath a surface of the substrate, the first layer having a second conductivity type; and a trench formed through the surface and passing through the first layer. The trench comprises an interior surface, a dielectric material lining the interior surface and a conductive material filling the lined trench. The first logic element is configured so that a predetermined voltage or higher applied between the conductive material and the first layer causes a breakdown within a region of the trench. A second one time, voltage programmable logic element is provided in a semiconductor substrate of first conductivity type that comprises a first layer formed in a surface of the substrate, the first layer having a second conductivity type; and a trench formed through the surface and passing through the first layer.

Abstract: A structure and method for simultaneously forming array structures and support structures on a substrate comprises forming the array structures to have a V-groove, forming the support structures to have a planar surface, and simultaneously forming a first oxide in the V-groove and a second oxide in the planar surface, wherein the first oxide is thicker than the second oxide.

Abstract: A semiconductor structure having a substrate, an insulator above a portion of the substrate, a conductor above the insulator; and at least two contact regions in the substrate on opposite sides of the portion of the substrate, wherein a voltage between the contact regions modulates a capacitance of the conductor.

Abstract: A logic circuit implementing a logic function and method of manufacture thereof. The logic circuit includes a series connection of two or more CMOS devices, at least one CMOS device having a threshold voltage at an input lower than a threshold voltage at an input of another of the CMOS devices. The CMOS logic circuit exhibits enhanced switching speed for logic operations and reduced leakage current when operating in an off-state. A logic family is built around the series connection of two or more devices having mixed voltage threshold inputs for enhanced switching speed and reduced off-current leakage.

Abstract: A composite, layered, integrated circuit formed by bonding of insulator layers on wafers provides for combination of otherwise incompatible technologies such as trench capacitor DRAM arrays and high performance, low power, low voltage silicon on insulator (SOI) switching transistors and short signal propagation paths between devices formed on respective wafer layers of a chip. In preferred embodiments, an SOI wafer is formed by hydrophilic bonding of a wafer over an integrated circuit device and then cleaving a layer of the second wafer away using implanted hydrogen and low temperature heat treatment. Further wafers of various structures and compositions may be bonded thereover and connections between circuit elements and connection pads in respective wafers made using short vias that provide fast signal propagation as well as providing more numerous connections than can be provided on chip edges.

Abstract: A method for forming depleted conductor regions in MOSFET arrays includes the steps of preparing a substrate, forming a conductor layer on the substrate, implanting a dopant species into the conductor layer, masking portions of the doped conductor layer, and counterdoping unmasked portions of the doped conductor layer to form said depleted conductor regions on the substrate. This method provides an alternative to dual gate oxide for MOSFETS wherein low voltage regions at doped layers are used for support devices and high voltage regions at counterdoped portions are used for memory arrays such as DRAM, EDRAM, SRAM and NVRAM. This method is also applicable for all chips requiring high and low voltage integral device operation.

Abstract: An integrated circuit assembly has pads of a chip electrically connected to pads of a substrate with rolling metal balls. A pliable material bonds the balls in movable contact with pads of the chip and substrate. Because the balls are relatively free to move, thermal expansion differences that would ordinarily cause enormous stresses in the attached joints of the prior art, simply cause rolling of the balls of the present invention, avoiding thermal stress altogether. Reliability of the connections is substantially improved as compared with C4 solder bumps, and chips can be safely directly mounted to such substrates as PC boards, despite substantial thermal mismatch.

Abstract: A method is provided for fabricating semiconductor devices having different properties on a common semiconductor substrate.

Abstract: Methods and apparatus for blowing and sensing antifuses are provided. Specifically, in a first aspect, a method is provided for changing the state of one of a plurality of antifuses by selecting one of the bank of antifuses and applying a high voltage to change the state of the selected antifuse. In second and third aspects, apparatus are provided for performing the method of the first aspect. In a fourth aspect, a method is provided for boosting a voltage that includes the steps of generating a first voltage within a first stage storage mechanism of a first stage voltage booster circuit, generating a second voltage equaling about twice the first voltage within a first and a second, second stage storage mechanism of a second stage voltage booster circuit, and generating about thrice the first voltage based on the second voltage of the second stage voltage booster circuit. In a fifth aspect, apparatus are provided for performing the method of the fourth aspect.

Abstract: A multi-function semiconductor device is provided. The device includes a bipolar transistor and an FET formed in parallel. A semiconductor substrate is provided on an insulating layer. A source/emitter region and a drain region are formed in the semiconductor substrate and border first opposite sides of a body region therebetween. A gate is formed above the substrate between the source/emitter region and the drain region to form an FET having three terminals including the gate, the source/emitter region, and the drain region. A collector region is formed in the substrate abutting the drain region and extending further under the gate and the drain region. A bipolar transistor having three terminals is formed including a base region, the source/emitter, and the collector region. A shortest distance between the collector region and the source/emitter region defines a base width.

Abstract: The present invention provides an integrated circuit which comprises a substrate having a plurality of device regions formed therein, said plurality of device regions being electrically isolated from each other by shallow trench isolation (STI) regions and said plurality of device regions each having opposing edges abutting its corresponding STI region; selected ones of said devices regions having a preselected first device width such that an oxide layer formed thereon includes substantially thicker perimeter regions, along said opposing edges, compared to a thinner central region that does not abut its corresponding STI region; and selected other ones of the device regions having a preselected device width substantially narrower in width than the first device width such that an oxide layer formed thereon includes perimeter regions, along opposing edges, that abut each other over its central region thereby preventing formation of a corresponding thinner central region.

Abstract: The disclosed invention provides a reduction of voltage noise or bounce in logic chips and does so in a practical way without requiting additional circuit elements that impact on circuit performance or speed. Broadly this reduction in voltage bounce is achieved by forcing the unused Input/Output (I/O) circuits, i.e., those chips not being activated, to serve as alterative paths to the voltage power supply used by the switching circuits. More particularly this is accomplished this by grouping the I/O points on the chips into logical, functional units such as data buses, control lines, the I/O points on switched circuits, i.e., those switched at high frequency and the I/O points on static circuits, i.e., non-switched and interconnecting and using the I/O points on the static circuits and the power supply drives coupled thereto as alternate pats to the power supply used by the switched circuits.

Abstract: A gap conductor structure for an integrated electronic circuit that may function as an electronic fuse device or as a low capacitance inter level signal line is integrated as part of the semi-conductor chip wiring. The gap conducting structure includes one or more air gap regions of predefined volume that fully or partially exposes a length of interlevel conductor layer in an IC. Alternately, the air gap region may wholly located within the dielectric region below a corresponding conductor and separated by insulator. When functioning as a fuse, the gap region acts to reduce thermal conductivity away from the exposed portion of the conductor enabling generation of higher heat currents in the conducting line with lower applied voltages sufficient to melt a part of the conducting line. The presence of gaps, and hence, the fuses, are scalable and may be tailored to the capacity of currents they must carry with the characteristics of the fuses defined by a circuit designer.

Abstract: Wafer test and burn-in is accomplished with state machine or programmable test engines located on the wafer being tested. Each test engine requires less than 10 connections and each test engine can be connected to a plurality of chips, such as a row or a column of chips on the wafer. Thus, the number of pads of the wafer that must be connected for test is substantially reduced while a large degree of parallel testing is still provided. The test engines also permit on-wafer allocation of redundancy in parallel so that failing chips can be repaired after burn-in is complete. In addition, the programmable test engines can have their code altered so test programs can be modified to account for new information after the wafer has been fabricated. The test engines are used during burn-in to provide high frequency write signals to DRAM arrays that provide a higher effective voltage to the arrays, lowering the time required for burn-in.

Abstract: A method and structure for manufacturing Charge-Coupled-Device (CCD) image pick-up devices. The method bonds a first wafer with a second wafer. The first wafer has a CCD layer on a first substrate, wherein the CCD layer includes a plurality of CCD pick-up image arrays. The CCD layer is thin, preferably in a range of 5 to 20 microns, while the substrate is relatively thicker (e.g., 300 microns). The first wafer also includes first conductive pads arranged in a pattern on a surface of the CCD layer such that each CCD array is conductively coupled to a plurality of the first conductive pads. The second wafer has a second substrate that includes a semiconductor material such as silicon, and second conductive pads according to the pattern on a surface of the second substrate. The first wafer is bonded with the second wafer to form a wafer composite, wherein the first conductive pads are joined to the second conductive pads in accordance with the pattern.

Abstract: Silicon is formed at selected locations on a substrate during fabrication of selected electronic components. A dielectric separation region is formed within the top silicon layer, and filled with a thermally conductive material. A liner material may be optionally deposited prior to depositing the thermally conductive material. In a second embodiment, a horizontal layer of thermally conductive material is also deposited in an oxide layer or bulk silicon layer below the top layer of silicon.