Abstract: A decimating memory includes a memory having addressable memory locations. The memory forms a plurality of registers, each of the registers including at least one addressable memory location. The plurality of registers form a forward shifting data section and a reverse shifting data section. A first decoder operates the registers in the forward shifting data section and all but a first of the registers in the reverse shifting data section as FIFO registers via read and write addressing of the addressable memory locations to input and output data samples. The read and write addressing of the addressable memory locations is offset with respect to one another to provide a decimation factor. A paintbrush decoder operates the first register in the reverse shifting data section as a LIFO register for reverse sequencing data samples within blocks of data samples received from the forward shifting data section. Each of the registers in the forward shifting and reverse shifting data sections provide an output.

Abstract: A sine/cosine generator with coarse and fine angles having compressed sine and cosine read only memories (ROMS) by use of symmetry of coarse angles about .pi./4 and, optionally, symmetry of fine angles about 0. The output of the ROMs directly feed multiplexers for utilization of the compressed storage. Addressing of complementary coarse angles is with one's complementing of the address and of complementary fine angles is with two's commplementing of the address. Fine sines and cosines are stored in recoded version for direct use in multipliers for computations using the sum of angles formulas.

Abstract: A sequencer including input structure for receiving and retaining sequential data which includes the sequence starting address, the number of blocks in the sequence, the number of words in a block, increment between blocks and increment between words, includes an adder connected between the input structure and an output device and includes a controller for selectively providing to the adders inputs one or more of the sequence starting address, increment between words, increment between blocks and the output of the output device as a function of the number of blocks in the sequence and the number of words in a block.

Abstract: A recoding method of two or more bit groups to reduce the number of partial products and their hardware implementation. Unique complementing scheme, pre-addition of complementing carriers and derivation of sign extensions also reduce hardware implementation as well as allowing the multiplier to handle any combination of input and output formats The principles are also applied to multiplier/accumulators and complex multipliers.

Abstract: A decimating memory includes a memory having addressable memory locations. The memory forms a plurality of registers, each of the registers including at least one addressable memory location. The plurality of registers form a forward shifting data section and a reverse shifting data section. A first decoder operates the registers in the forward shifting data section and all but a first of the registers in the reverse shifting data section as first in first out registers via read and write addressing of the addressable memory locations to input and output data samples. The read and write addressing of the addressable memory locations is offset with respect to one another to provide a decimation factor. A paintbrush decoder operates the first register in the reverse shifting data section as a last in first out register for reverse sequencing data samples within blocks of data samples received from the forward shifting data section.

Abstract: A sin/cos generator which stores values for sin X and cos X, multiplies the sin X and cos X by the value sin Y to produce partial products -sin Y sin X and sin Y cos X and adds the partial products sin Y cos X to sin X to produce sin (X+Y) and adds the partial products -sin Y sin X to cos X to produce cos (X+Y). The values of sin X and cos X are stored for a single quadrant without sign designation and quadrant control is provided to complement the appropriate values of sin X and cos X before adding and multiplying. The complementing forms the one's complement and adds a 1 in the least significant bit to form the two's complement.

Abstract: Forming the shift register as a plurality of memory locations in a memory array where the input port for writing into the memory and the output port for reading out of the memory are sequenced along the array. Thus the input and output ports are shifted with respect to the array instead of the information shifting with respect to fixed input and output ports. The length or number stages of the shift register may be varied by changing the displacement or offset of the output or reading port to the input or writing port in the sequence.

Abstract: A superalloy article is fabricated by casting a high melting temperature superalloy composition and then refurbishing the primary defects that are found in the surface of the cast piece. The article is refurbished by excising the primary defects and a surrounding portion of metal by grinding, filling the excised volume with metal of the same composition as the cast article by welding or a similar technique, smoothing the surface around any resulting filler metal defects, and applying a cladding powder to the surface from which the filler metal defects are removed. The cladding powder is applied by painting a binder onto the surface and then dusting cladding powder onto the binder before it has dried. The cladding powder is a mixture of particles of a high melting temperature superalloy and particles of a lower melting temperature metal. The article is heated to a preselected temperature, depending on the alloy, to melt and subsequently solidify the cladding powder.

Abstract: A double level conductive structure is provided wherein one conductor layer permits impurities to pass therethrough in a given impurity introduction steph while double conductor level portion substantially prevents such impurities from passing therethrough due to a greater combined resistance to impurity penetration.

Abstract: Each cross-point includes a first and second storage device with the next cycle information being stored in the first storage device and transferred to the second storage device which has the present cycle information. The output of the second storage means is used in combination with a second controlling input to control the switch or logic at a cross-point. In one embodiment, the cross-point state is stored in the storage devices and is combined with the input data to provide an output on the data output line. In another embodiment, input data is stored in the storage devices and is combined with input state selects to provide an output on the data output line.

Abstract: A memory device for a content addressable memory is configured of a pair of multibit memory cells which permits the memory to be programmably readable on an individual bit basis, whereby the memory may be selectively programmed to be fully content addressable, partially content addressable, or non-content addressable. The memory device is coupled to a complementary bit line pair and has a pair of word enable lines coupled to address lines and a respective row output line, the state of which is monitored during an associative read operation. Data is stored in a respective memory device in the form of complementary bit codes, individual components of which are written into the memory cells. The participation of each memory device during an associative read operation is controlled by means of a set of switching circuits that are coupled to each memory cell, the bit lines and the output line.

Abstract: An adder comprising a tree-based carry structure, wherein the maximum fanout from any gate in the carry structure is three. When calculating optimized fanout, it is necessary to consider input capacitance to the following stage. In minimizing propagation delay, it is necessary to consider loading and the number of stages. It has been recognized that optimum fanout of e results in optimized propagation through the adder, thus fanout of three is the closest whole number. A cell has been designed which includes the necessary and sufficient circuitry for building multicell adders in a highly optimized structure. The cell provides individually accessible components and dedicated components for optimum layout in the end product.

Abstract: A laser plasma spray apparatus for depositing a feed material onto a substrate includes a nozzle having a plasma confinement chamber into which a laser beam is focused, the focal point being at a distance sufficiently far from the substrate that the substrate is not melted. Finely divided feed material in a carrier gas flow is fed axially into the confinement chamber along the direction of the laser beam and melted in the plasma formed in the interaction of the laser beam, the feed material, and the gas at the focal point. The melted feed material is then directed to deposit onto the substrate, while the plasma energy is largely confined within the apparatus by the confinement chamber and a constriction in the flow path upstream of the confinement chamber.

Abstract: A low power programmable delay circuit produces an output pulse having multiple-variable signal characteristics that are independent of power supply functions and wafer processing parameters. The delay circuit employs a timing pulse generator which initiates the generation of a timing pulse in accordance with a prescribed logical combination of an input pulse and a control logic level. The timing pulse generator contains a time constant control circuit that establishes the rate of change of the leading and trailing edges of the timing pulse. The timing pulse is coupled to a Schmitt trigger circuit to produce a pulse having sharply defined leading and trailing edges the times of occurrence of which are determined by the trigger threshold of the Schmitt trigger circuit. This Schitt trigger output pulse is logically combined with the original input signal to produce a programmably delayed output pulse.

Abstract: Integrated circuits with vertical isolated trenches are radiation hardened by providing vertical gate segments, preferably, of doped polycrystalline silicon, in the trenches and connected at the bottom of the trenches to a region of the same conductivity type. The surface devices may be complementary and the vertical gates may also be complementarily doped. A method of fabrication is described for a single crystal wafer, as well as SOI.

Abstract: First and second input gates and an input inverter are provided for preprocessing respectively a plurality of input signals and an additional input signal, in addition to a carry gate and a sum gate. The first input gate is connected to each of a plurality of input bits for providing a logic low output only when all of its inputs are a logic high. The second input gate is connected to the plurality of input bits for providing a logic high only when all of its inputs are a logic low. The carry gate has three inputs and provides a carry-out logic high output when either (a) its first input from the first logic gate is a logic low; or (b) when both the second input from the second input gate and the third input from the inverter are a logic low.

Abstract: A compact vertical contact has lateral space requirements in the fabrication of semiconductor devices and is compatible with highly planarized processes. The contact is made from a foundation region having a top surface to an overlying layer separated from the foundation region by a dielectric. The overlying layer may be contacted at an edge rather than on its top surface in order to reduce the lateral expanse of the contact.

Abstract: Integrated circuits with vertical isolated trenches are radiation hardened by providing vertical gate segments, preferably, of doped polycrystalline silicon, in the trenches and connected at the bottom of the trenches to a region of the same conductivity type. The surface devices may be complementary and the vertical gates may also be complementarily doped. A method of fabrication is described for a single crystal wafer, as well as SOI.

Abstract: An ALU comprising a tree-based carry structure, wherein the maximum fanout from any gate in the carry structure is three. When calculating optimized fanout, it is necessary to consider input capacitance to the following stage. In minimizing propagation delay, it is necessary to consider loading and the number of stages. It has been recognized that optimum fanout of results in optimized propagation through the ALU, thus fanout of three is the closest whole number. A cell has been designed which includes the necessary and sufficient circuitry for building multicell ALU's in a highly optimized structure. The cell provides individually accessible components and dedicated components for optimum layout in the end product.

Abstract: A current compensated precharged bus including tracking circuit as a part of a latch in a pre-charge circuit for maintaining a fixed deactivation voltage level of the latch. The tracking circuit includes an on-tracking circuit connected to the latch for tracking the characteristics of one of the input devices of the logic circuit being activated and an off-tracking circuit connection to the latch for tracking the characteristics of all the input elements of the logic circuit being deactivated. The latch includes a pull-up transistor, and a deactivation element, connected to the bus for sensing the voltage on the bus and generating a latch deactivation signal when the deactivation voltage level of the deactivation device is exceeded.