Abstract: A process for the formation of a compact vertical contact having reduced lateral space requirements yet compatible with highly planarized semiconductor manufacturing processes. The contact is made from a foundation region having a top surface to an overlying layer separated from the foundation region by a dielectric. The overlying layer can be contacted on its edge rather than on its top surface in order to reduce the lateral expanse of the contact.

Abstract: An improved mixture of alloy powders is provied for use in treating a preselected article alloy, for example, to repair or join multiple components of the article. The mixture has at least three distinct groups of alloy powders which together define a mixture composition range, with each alloy powder of the groups characterized by a composition and melting range different from the others and from the article alloy. In a preferred form, the mixture composition range comprises, by weight, 15-30% Cr, 1.5-6% W, 0.4-4% Al, 1-11% Ti, 1-6% Ta, up to 1.5% B, up to 0.5% Si, up to 0.2% Zr, up to 3% Mo, up to 0.3% Hf, up to 6% Cb, up to 2% Re, with the balance selected from Co and Ni along with incidental impurities.

Abstract: An output buffer initially operating its output transistors in a constant current mode in response to an input signal transition and subsequently operating its output transistors in a constant voltage drive mode as the output approaches the desried output level. The control electrode of the output transistor is controlled by a switchable voltage divider or current mirror. The control of an output transistor may not be activated until the other output transistor is turned off to prevent having both output devices on at the same time.

Abstract: A serial fast propagation transmission switch responsive to a propagate input control signal to transmit a signal from the input to the output terminal in combination with a double inverting logic parallel to the transmission switch to limit the line impedance to a single stage impedance subsequent to the serial transmission.

Abstract: An address decoder architecture capable of having a precharge signal for the word line coincident with the enabling of the decoder section to reduce the operating cycle. The word line latch is separate and distinct from the word line driver such that disablement of the word line driver during readdressing of the enabled decoder will not effect the portion of the cycle that the word line maintains its logic state.

Abstract: A method of setting a memory array to a common logic value by activating all the line switches by the precharge device for the duration of a word signal and simultaneously applying the common logic value directly to all the bit lines.

Abstract: An ALU having improved propagate and generate signal section as well as carry and sum logic section to decrease the propagation delays. The propagate and generate signal section is specifically designed to be used with a dual ported RAM such that transition of the precharged RAM outputs to the desired outputs are used to trigger the logic. Latches, which are an integral part of the output of the propagate and generate signal section and are latched by the high/low transition of the output and reset by precharge signal, are used in combination with a special control sequence of the logic select of the propagate and generate section to isolate the latch and output such that one of the buses though the ALU may be used as a bidirectional bus so that the ALU may write back into the RAM without intermediate registers or latches.

Abstract: An integrated structure including a program counter, a memory management structure and an incrementer interconnected by an internal bus such that the logic value of the program counter may be read into the memory management register and the program counter can be incremented depending upon the value of the pre-incremented program counter logic level and an increment signal from the previous stage. External access to the program counter and the memory management register are provided by external buses. A sense amplifier is also provided so as to maintain the value of the pre-incremented program counter on the internal rail allowing the memory management register to be disconnected therefrom during the increment cycle.

Abstract: A powder mixture for use in a method of repairing a superalloy article includes first and second Ni base superalloy powders. The first powder, characterized by superior hot corrosive resistance along with good oxidation resistance and the substantial absence of melting point depressants selected from Si and B greater than normal impurity levels, is included in the range of 30-70 wt % of the mixture. The second powder has a composition substantially within the same composition range as that of the first powder with the inclusion, by wt, of 0.5-5% B and up to 6% Si.

Abstract: An improved integrated ROM/PLA structure which is capable of simultaneous PLA and ROM addressing substantially reduces the number of tests needed to verify the complete structure. The OR gate matrix and the ROM addressing mode of the AND gate matrix are verified using the ROM addressing mode. The PLA addressing mode is tested by the simultaneously using the ROM and PLA addressing modes to individually activate the AND gates. The AND gates are then tested with the DON'T CARE address lines at a first state and then a second logic state. The test sequence then includes complementing the CARE lines one at a time.The ROM/PLA structure is also improved to include two input structures providing parallel inputs to the OR matrix and dedicated first and second ROM portions of the OR matrix. The output logic is modified so as to merge the literal from the input macroinstruction into the output microinstruction.

Abstract: A loop controller transmits data to and receives data from a plurality of I/O ports on a TDM serial loop by generating a plurality of frames which include a frame control field followed by a plurality of dedicated time slot fields. Each time slot field includes an inbound data control bit or bits followed by a data field followed by an outbound data control bit or bits. The I/O port inputs and outputs data in its dedicated data field as dictated by the respective data control bit. The loop controller and I/O ports monitor the data control bit to request data, indicate insertion of data, indicate receipt of the data and acknowledge the receipt indication to achieve a complete handshake. During an initialization frame, the I/O ports set themselves into primary and secondary data modes based on sensing a prior I/O port with the same dedicated time slot.

Abstract: An interface circuit including a FET inverter with its N channel device being part of the controlled leg of a first current mirror and its P channel device being part of the controlled leg of a second current mirror. The operating point of the inverter is the reference signal applied on the input to the current mirrors. The controlled leg of the first current mirror includes a variable current source responsive to the input signal and the controlled leg of the second current mirror includes a variable current sink for improving the response time of the inverter and compensates the inverter for manufacturing tolerances.

Abstract: A CMOS amplifier having a pair of CMOS load and amplifying devices connected in series, two parallel pairs of CMOS devices with interconnected gates to form current mirrors and connected to the gate of the load MOS device to compensate the gain for variations in power supply voltage, temperature and transistor parameters, a feedback MOS device having its source-drain path connected between the junction of the load and amplifying MOS and the gate of the amplifying MOS to provide nonlinear, negative feedback, and a resistor connected in parallel with the feedback MOS device to establish an initial self-biasing voltage level for the amplifying MOS below the threshold voltage of the feedback MOS.

Abstract: A property, such as ductility, mechanical strength and increased remelt temperature, of an alloy, for example one which includes an element such as Si or B, or both, is improved by depletion of such an element through the alloy surface. This is accomplished by exposing the alloy surface, one common form of which is a brazing alloy, to gaseous ions such as fluoride ions, while heating the alloy at a temperature which is not detrimental to the alloy or members associated with the alloy. Heating is conducted for a time sufficient for such elements, for example those selected from Si and B, included as a melting point depressant, to diffuse to the surface of the alloy and to react with the gaseous ions to form a gaseous compound of the element. Such gaseous compound then separates from the surface, thereby depleting the alloy of the element and improving at least one property.

Abstract: Apparatus for measuring an aircraft's horizontal speed and height above ground without the need for airborne cooperative devices. Two ground level TV cameras separated by a measured distance and pointed at zenith are placed in line with the projection of the expected path of the aircraft. Speed is determined by measuring the time that it takes the aircraft to travel between the fields of view of the two TV cameras using zenith crossings as the reference points. Height is determined by correlating the speed with the time required to cross the field of view of either of the two cameras.