Abstract: A structure of a circuitry substrate for securing an area from tampering is disclosed. The structure includes a circuitry substrate with at least one of a top tamper enclosure and a bottom tamper enclosure covering a component in a protected area of the circuitry substrate. The top and bottom tamper enclosures are adhesively bonded to a surface of the circuitry substrate, and a tear initiation site is added to a side of the perimeter of circuitry substrate bordering the protected area that includes at least one tamper enclosure, such that the tear initiation site is located and configured to enable propagation of a delamination of at least one internal layer of the circuitry substrate and a severing of a security circuit when a removal force is applied to the at least one of the top tamper enclosure and the bottom tamper enclosure.

Abstract: A laminate carrier-like module lid including multiple laminate layers of non-conductive materials stacked one atop another, sensor circuitry embedded within the laminate carrier-like module lid, the sensor circuitry providing a continuous electrical circuit surrounding the electronic components of the multi-chip module package, and thermal circuitry embedded within the laminate carrier-like module lid, the thermal circuitry comprising solid copper traces to thermally conduct heat from the electronic components of the multi-chip module package.

Abstract: A tamper detection system may include organic material and a tamper detection circuit embedded in the organic material. A portion of the organic material is ablated away to form an incision in the organic material. A portion of the tamper detection circuit obstructs a fragment of the ablation path. The tamper detection circuit remains intact. The incision enables a gas flow between a first side of the organic material and a second side of the organic material.

Abstract: A laminate carrier-like module lid including multiple laminate layers of non-conductive materials stacked one atop another, sensor circuitry embedded within the laminate carrier-like module lid, the sensor circuitry providing a continuous electrical circuit surrounding the electronic components of the multi-chip module package, and thermal circuitry embedded within the laminate carrier-like module lid, the thermal circuitry comprising solid copper traces to thermally conduct heat from the electronic components of the multi-chip module package.

Abstract: Aspects include a cryptographic hardware security module having a secure embedded heat pipe and methods for assembling the same. The cryptographic hardware security module can include a printed circuit board having one or more components. The cryptographic hardware security module can further include an encapsulation structure having a top can and a bottom can. The top can is fixed to a first surface of the printed circuit board and the bottom can is fixed to second surface of the printed circuit board opposite the first surface. A heat pipe is positioned between the top can and the component. The heat pipe includes two or more 180-degree bends. A portion of the heat pipe extends beyond a secure region of the encapsulation structure.

Abstract: A tamper detection system may include organic material and a tamper detection circuit embedded in the organic material. A portion of the organic material is ablated away to form an incision in the organic material. A portion of the tamper detection circuit obstructs a fragment of the ablation path. The tamper detection circuit remains intact. The incision enables a gas flow between a first side of the organic material and a second side of the organic material.

Abstract: A uniform thickness flex circuit is taught that uses more than one dielectric layer. A first dielectric layer is more flexible and capable of reliably bending at a radius of curvature at which a second dielectric layer cannot be reliably bent. The second dielectric layer has at least one more desirable electrical characteristic than the first dielectric area, for example leakage. Use of the uniform thickness flex circuit to protect sensitive material in an electronic enclosure is also described.

Abstract: A uniform thickness flex circuit is taught that uses more than one dielectric layer. A first dielectric layer is more flexible and capable of reliably bending at a radius of curvature at which a second dielectric layer cannot be reliably bent. The second dielectric layer has at least one more desirable electrical characteristic than the first dielectric area, for example leakage. Use of the uniform thickness flex circuit to protect sensitive material in an electronic enclosure is also described.

Abstract: Provided is a method for masking a sensitive signal by injecting noise into planes of a printed circuit board (PCB). The method comprises detecting, by a secondary integrated circuit (IC), a noise signal on a shared plane of a PCB that includes the secondary IC. The noise signal may be analyzed to determine the characteristics of the noise signal. A masking signal may be generated based on the characteristics. The masking signal may then be injected onto the shared plane.

Abstract: The present invention discloses a method for managing priority-arbitrated access to a set of one or more computational engines of a physical computing device. The method includes providing a multiplexer module and a network bus in the physical computing device, wherein the multiplexer module is connected to the network bus. The method further includes receiving, by the multiplexer module, a first data processing request from a driver and inferring, by the multiplexer module, a first priority class from the first data processing request according to at least one property of the first data processing request. The method further includes manipulating, by the multiplexer module, a priority according to which the physical computing device handles data associated with the first data processing request in relation to data associated with other data processing requests, wherein the priority is determined by the first priority class.

Abstract: A method to fabricate a tamper respondent assembly is provided. The tamper respondent assembly includes an electronic component and an enclosure at least partly enclosing the electronic component. A piezoelectric sensor is integrated in the enclosure. The integrating includes providing a base structure that includes a first conductive layer, depositing a piezoelectric layer on the first conductive layer, covering the piezoelectric layer with a second conductive layer, and providing sensing circuitry for observing sensing signals of the piezoelectric layer. The piezoelectric layer includes a plurality of nanorods. Aspects of the invention further relates to a corresponding assembly and a corresponding computer program product.

Abstract: The present invention discloses a method for managing priority-arbitrated access to a set of one or more computational engines of a physical computing device. The method includes providing a multiplexer module and a network bus in the physical computing device, wherein the multiplexer module is connected to the network bus. The method further includes receiving, by the multiplexer module, a first data processing request from a driver and inferring, by the multiplexer module, a first priority class from the first data processing request according to at least one property of the first data processing request. The method further includes manipulating, by the multiplexer module, a priority according to which the physical computing device handles data associated with the first data processing request in relation to data associated with other data processing requests, wherein the priority is determined by the first priority class.

Abstract: Tamper-respondent assemblies and fabrication methods are provided which utilize liquid crystal polymer layers in solid form. The tamper-respondent assemblies include a circuit board, and an enclosure assembly mounted to the circuit board to enclose one or more electronic components coupled to the circuit board within a secure volume. The assembly includes a tamper-respondent sensor that is a three-dimensional multilayer sensor structure, which includes multiple liquid crystal polymer layers, and at least one tamper-detect circuit. The at least one tamper-detect circuit includes one or more circuit lines in a tamper-detect pattern disposed on at least one liquid crystal polymer layer of the multiple liquid crystal polymer layers. Further, a monitor circuit is provided disposed within the secure volume to monitor the at least one tamper-detect circuit of the tamper-respondent sensor for a tamper event.

Abstract: Tamper-respondent assemblies and fabrication methods are provided which incorporate enclosure-to-circuit board protection. The tamper-respondent assemblies include a circuit board, and an enclosure mounted to the circuit board along an enclosure-to-board interface. The enclosure facilitates enclosing at least one electronic component coupled to the circuit board within a secure volume. A tamper-respondent electronic circuit structure facilitates defining the secure volume, and includes one or more tamper-detect circuits including at least one conductive trace disposed, at least in part, within the enclosure-to-board interface. The conductive trace(s) includes stress rise regions to facilitate tamper-detection at the enclosure-to-board interface. An adhesive is provided to secure the enclosure to the circuit board. The adhesive contacts, at least in part, the conductive trace(s) of the tamper-detect circuit(s) at the enclosure-to-board interface, including at the stress rise regions of the conductive trace(s).

Abstract: The present invention relates to a method to fabricate a tamper respondent assembly. The tamper respondent assembly includes an electronic component and an enclosure fully enclosing the electronic component. The method includes printing, by a 3-dimensional printer, a printed circuit board that forms a bottom part of the enclosure and includes a first set of embedded detection lines for detecting tampering events and signal lines for transferring signals between the electronic component and an external device. The electronic component is assembled on the printed circuit board, and a cover part of the enclosure is printed on the printed circuit board. The cover part includes a second set of embedded detection lines. Sensing circuitry can be provided for sensing the conductance of the first set of embedded detection lines and the second set of embedded detection lines to detect tampering events.

Abstract: Provided is a method for masking a sensitive signal by injecting noise into planes of a printed circuit board (PCB). The method comprises detecting, by a secondary integrated circuit (IC), a noise signal on a shared plane of a PCB that includes the secondary IC. The noise signal may be analyzed to determine the characteristics of the noise signal. A masking signal may be generated based on the characteristics. The masking signal may then be injected onto the shared plane.

Abstract: A method includes determining, by a tracker controller of a hardware security module, that a first processor has submitted a first request to access a computing resource. The method also includes determining, by the tracker controller, whether the first request and a second request both request access to the same computing resource. The second request is submitted by a second processor. The method also includes preventing access to the computing resource based on a determination that the first request and the second request do not request access to the same computing resource. The method also includes permitting access to the computing resource based on a determination that the first request and the second request both request access to the same computing resource.

Abstract: The present disclosure relates to a computer-implemented method for controlling operation of multiple computational engines of a physical computing device. The computer-implemented method includes providing a multiplexer module in the device, the multiplexer module including a first and second memory region. The multiplexer module may receive from a first driver at the multiplexer module a data processing request to be processed by a first set of one or more computational engines of the computational engines. Subsequent to receiving the data processing request, the multiplexer module may assign a request sub-region of the first region and a response sub-region of the second region to the first driver. Data indicative of the request sub-region and the response sub-region may be submitted to the first driver. Results of processing the request may be received at the response sub-region.

Abstract: The present disclosure relates to a computer-implemented method for controlling operation of multiple computational engines of a physical computing device. The computer-implemented method includes providing a multiplexer module in the device, the multiplexer module including a first and second memory region. The multiplexer module may receive from a first driver at the multiplexer module a data processing request to be processed by a first set of one or more computational engines of the computational engines. Subsequent to receiving the data processing request, the multiplexer module may assign a request sub-region of the first region and a response sub-region of the second region to the first driver. Data indicative of the request sub-region and the response sub-region may be submitted to the first driver. Results of processing the request may be received at the response sub-region.

Abstract: System, methods, and media are provided for enforcing segmentation of multi-tenant data. An example method includes informing hardware of direct memory access (DMA) segmented regions, in which the hardware is informed of software-specified size and count parameters relating to DMA windows. Identifying an originating DMA window for each DMA descriptor and referenced data. Verifying that contents of one or more DMA transfers are entirely from memory controlled by a single process. Setting DMA window-describing registers based the software-specified size and count parameters. Enforcing restrictions, based on the DMA window-describing registers, for DMA requests relating to the DMA windows as DMA requests are received.