Abstract: In some embodiments, a computer system applies a time of day setting to a virtual environment. In some embodiments, the time of day setting is updated based on an event. In some embodiments, a computer system displays content in an expanded display mode. In some embodiments, computer systems join a communication session while maintaining display of respective environments. In some embodiments, a computer system moves a portal based on user movement. In some embodiments, computer systems share a virtual environment. Computer systems can display media with simulated lighting. Computer systems can share an environment. In some embodiments, a computer system selects a position relative to content. A computer system can present representations of communication session participants based on content. A computer system can present user interfaces to control visual appearances of an environment including media. Computer systems can change an appearance of an environment based on environmental modes.

Abstract: Systems and methods for reducing problems and disadvantages associated with power consumption in memory devices are disclosed. In accordance with one embodiment of the present disclosure, a method for improving performance and reducing power consumption in memory may include tracking whether individual units of a memory system are active or inactive. The method may also include placing inactive individual units of the memory system in a self-refresh mode, such that the inactive individual units self-refresh their contents. The method may further include placing active individual units of the memory system in a command-based refresh mode, such that the active individual units are refreshed in response to a received command to refresh their contents.

Abstract: A performance optimization system includes a plurality of system components. A monitoring plug-in and a configuration plug-in are coupled to each of the plurality of system components. A monitoring engine receives monitoring information for each of the plurality of system components from their respective monitoring plug-in. A configuration engine sends configuration setting information to each of the plurality of system components through their respective configuration plug-ins. A performance optimization engine receives the monitoring information from the monitoring engine, determines a policy associated with the monitoring information and, in response, retrieves configuration setting information that is associated with the policy and sends the configuration setting information to the configuration engine in order to change the configuration of at least one of the plurality of system components.

Abstract: Systems and methods for reducing problems and disadvantages associated with power consumption in memory devices are disclosed. In accordance with one embodiment of the present disclosure, a method for improving performance and reducing power consumption in memory may include tracking whether individual units of a memory system are active or inactive. The method may also include placing inactive individual units of the memory system in a self-refresh mode, such that the inactive individual units self-refresh their contents. The method may further include placing active individual units of the memory system in a command-based refresh mode, such that the active individual units are refreshed in response to a received command to refresh their contents.

Abstract: A performance optimization system includes a plurality of system components. A monitoring plug-in and a configuration plug-in are coupled to each of the plurality of system components. A monitoring engine receives monitoring information for each of the plurality of system components from their respective monitoring plug-in. A configuration engine sends configuration setting information to each of the plurality of system components through their respective configuration plug-ins. A performance optimization engine receives the monitoring information from the monitoring engine, determines a policy associated with the monitoring information and, in response, retrieves configuration setting information that is associated with the policy and sends the configuration setting information to the configuration engine in order to change the configuration of at least one of the plurality of system components.

Abstract: An apparatus including a first connector configured to fit into a first socket in a processing system, the first connector and first socket conforming to a first standard, a second socket configured to accept a memory module therein, the second socket and the memory module conforming to a second standard, a memory buffer module communicatively coupled to the first connector and the second socket, the memory buffer module configured to receive signals associated with the first standard from the first connector and output signals associated with the second standard to the second socket, and a virtualization module communicatively coupled to the memory buffer module, the first connector, and the second socket, the virtualization module configured to receive first initialization data associated with the second standard from the second socket and output second initialization data associated with the first standard to the processing system.

Abstract: A performance optimization system includes a plurality of system components. A monitoring plug-in and a configuration plug-in are coupled to each of the plurality of system components. A monitoring engine receives monitoring information for each of the plurality of system components from their respective monitoring plug-in. A configuration engine sends configuration setting information to each of the plurality of system components through their respective configuration plug-ins. A performance optimization engine receives the monitoring information from the monitoring engine, determines a policy associated with the monitoring information and, in response, retrieves configuration setting information that is associated with the policy and sends the configuration setting information to the configuration engine in order to change the configuration of at least one of the plurality of system components.

Abstract: An apparatus including a first connector configured to fit into a first socket in a processing system, the first connector and first socket conforming to a first standard, a second socket configured to accept a memory module therein, the second socket and the memory module conforming to a second standard, a memory buffer module communicatively coupled to the first connector and the second socket, the memory buffer module configured to receive signals associated with the first standard from the first connector and output signals associated with the second standard to the second socket, and a virtualization module communicatively coupled to the memory buffer module, the first connector, and the second socket, the virtualization module configured to receive first initialization data associated with the second standard from the second socket and output second initialization data associated with the first standard to the processing system.

Abstract: A power input utilization system includes a plurality of components and a plurality of power input connectors. A power utilization engine is coupled between the plurality of power input connectors and the plurality of components. The detect a power input to the plurality of power input connectors and determine a power input characteristic for the power input. The power utilization engine is also operable to use the power input characteristic to determine a plurality of operation characteristics for the plurality of components. The power utilization engine is also operable to operate the plurality of components using on the power input and the plurality of operation characteristics.

Abstract: In accordance with the present disclosure, a system and method for performing a system memory save in tiered or cached storage during transition to a decreased power state is disclosed. As disclosed herein, the system incorporating aspects of the present invention may include a flash or other nonvolatile memory such as a solid-state drive, volatile memory, and at least one alternate storage media. Upon transition to a decreased power state, at least some of the data in the solid-state drive, for example, may be transferred to the at least one alternate storage media. After the SSD data is transferred, data stored in volatile system memory, such as a system context, may be transferred to the SSD memory. With the system context saved in SSD memory, power to the volatile system memory may be turned off.

Abstract: A method of selectively enabling error checking in an information handling system, including receiving information indicating that data associated with a first memory portion in a system memory should be subject to error checking during transmission between the memory controller and the system memory and indicating that data associated with a second memory portion in the system memory should be free of error checking during transmission between the memory controller and the system memory, receiving a memory access request directed to one of the first and second memory portions, transmitting data between the memory controller and the system memory in response to the memory access request, and selectively performing an error checking technique on the transmitted data based on the information.

Abstract: A method of memory controller-independent memory mirroring includes providing a mirroring association between a first memory segment and a second memory segment that is independent of a memory controller. A memory buffer receives data from the memory controller that is directed to a first memory location in the first memory segment. The memory buffer writes the data, independent of the memory controller, to both the first memory segment and the second memory segment according to the mirroring association. The memory buffer receives a plurality of read commands from the memory controller that are directed to the first memory location in the first memory segment and, in response, reads data from an alternating one of the first memory segment and the second memory segment and stores both first data from the first memory segment and second data from the second memory segment.

Abstract: A method of selectively enabling error checking in an information handling system, including receiving information indicating that data associated with a first memory portion in a system memory should be subject to error checking during transmission between the memory controller and the system memory and indicating that data associated with a second memory portion in the system memory should be free of error checking during transmission between the memory controller and the system memory, receiving a memory access request directed to one of the first and second memory portions, transmitting data between the memory controller and the system memory in response to the memory access request, and selectively performing an error checking technique on the transmitted data based on the information.

Abstract: A low power write journaling storage system may be part of an information handling system that includes a system processor and a system memory that is coupled to the system processor. The low power write journaling storage system is coupled to the system processor and includes a non-volatile solid state memory system. A first processing element in the low power write journaling storage system is operable, while the storage system is in a storage system first mode, to journal write commands in the non-volatile solid state memory system. A second processing element in the low power write journaling storage system is operable, while the storage system is in a storage system second mode that may cause the low power write journaling storage system to consume more power than when in the storage system first mode, to execute the write commands journaled in the non-volatile solid state memory system.

Abstract: An information handling system (IHS) includes a memory controller, a memory device, and firmware. A failing memory region and a spare memory region are included on the memory device. A memory buffer in the memory device is coupled to the failing memory region and the spare memory region. The memory buffer is operable to perform copy operations without instruction from the memory controller in order to copy data from the failing memory region to the spare memory region in response to firmware operations performed by the firmware. Firmware operations may include instructing the memory controller to produce additional refresh or calibration operation time periods, or providing an instruction to perform a data transfer operation to the spare memory region. The memory buffer is also operable to route requests from the memory controller to one of the failing memory region and the spare memory region during the copy operations.

Abstract: An apparatus including a first connector configured to fit into a first socket in a processing system, the first connector and first socket conforming to a first standard, a second socket configured to accept a memory module therein, the second socket and the memory module conforming to a second standard, a memory buffer module communicatively coupled to the first connector and the second socket, the memory buffer module configured to receive signals associated with the first standard from the first connector and output signals associated with the second standard to the second socket, and a virtualization module communicatively coupled to the memory buffer module, the first connector, and the second socket, the virtualization module configured to receive first initialization data associated with the second standard from the second socket and output second initialization data associated with the first standard to the processing system.

Abstract: An apparatus including a first connector configured to fit into a first socket in a processing system, the first connector and first socket conforming to a first standard, a second socket configured to accept a memory module therein, the second socket and the memory module conforming to a second standard, a memory buffer module communicatively coupled to the first connector and the second socket, the memory buffer module configured to receive signals associated with the first standard from the first connector and output signals associated with the second standard to the second socket, and a virtualization module communicatively coupled to the memory buffer module, the first connector, and the second socket, the virtualization module configured to receive first initialization data associated with the second standard from the second socket and output second initialization data associated with the first standard to the processing system.

Abstract: A method of selectively enabling error checking in an information handling system, including receiving information indicating that data associated with a first memory portion in a system memory should be subject to error checking during transmission between the memory controller and the system memory and indicating that data associated with a second memory portion in the system memory should be free of error checking during transmission between the memory controller and the system memory, receiving a memory access request directed to one of the first and second memory portions, transmitting data between the memory controller and the system memory in response to the memory access request, and selectively performing an error checking technique on the transmitted data based on the information.

Abstract: An apparatus including a first connector configured to fit into a first socket in a processing system, the first connector and first socket conforming to a first standard, a second socket configured to accept a memory module therein, the second socket and the memory module conforming to a second standard, a memory buffer module communicatively coupled to the first connector and the second socket, the memory buffer module configured to receive signals associated with the first standard from the first connector and output signals associated with the second standard to the second socket, and a virtualization module communicatively coupled to the memory buffer module, the first connector, and the second socket, the virtualization module configured to receive first initialization data associated with the second standard from the second socket and output second initialization data associated with the first standard to the processing system.

Abstract: Systems and methods for reducing problems and disadvantages associated with power consumption in memory devices are disclosed. A method for reducing power consumption in memory may include tracking, by an operating system executing on a processor, one or more logical units of a memory system that are in use. The method may also include setting, by the operating system, a variable indicating a portion of the memory system in use based on the logical units of the memory system in use. The method may additionally include refreshing one or more of the one or more logical units of the memory system based on the variable.