Abstract: An information handling system (IHS) includes a memory controller, a memory device, and firmware. A failing memory region and a spare memory region are included on the memory device. A memory buffer in the memory device is coupled to the failing memory region and the spare memory region. The memory buffer is operable to perform copy operations without instruction from the memory controller in order to copy data from the failing memory region to the spare memory region in response to firmware operations performed by the firmware. Firmware operations may include instructing the memory controller to produce additional refresh or calibration operation time periods, or providing an instruction to perform a data transfer operation to the spare memory region. The memory buffer is also operable to route requests from the memory controller to one of the failing memory region and the spare memory region during the copy operations.

Abstract: A performance optimization system includes a plurality of system components. A monitoring plug-in and a configuration plug-in are coupled to each of the plurality of system components. A monitoring engine receives monitoring information for each of the plurality of system components from their respective monitoring plug-in. A configuration engine sends configuration setting information to each of the plurality of system components through their respective configuration plug-ins. A performance optimization engine receives the monitoring information from the monitoring engine, determines a policy associated with the monitoring information and, in response, retrieves configuration setting information that is associated with the policy and sends the configuration setting information to the configuration engine in order to change the configuration of at least one of the plurality of system components.

Abstract: A power input utilization system includes a plurality of components and a plurality of power input connectors. A power utilization engine is coupled between the plurality of power input connectors and the plurality of components. The detect a power input to the plurality of power input connectors and determine a power input characteristic for the power input. The power utilization engine is also operable to use the power input characteristic to determine a plurality of operation characteristics for the plurality of components. The power utilization engine is also operable to operate the plurality of components using on the power input and the plurality of operation characteristics.

Abstract: Systems and methods for reducing problems and disadvantages associated with power consumption in memory devices are disclosed. A method for reducing power consumption in memory may include tracking, by an operating system executing on a processor, one or more logical units of a memory system that are in use. The method may also include setting, by the operating system, a variable indicating a portion of the memory system in use based on the logical units of the memory system in use. The method may additionally include refreshing one or more of the one or more logical units of the memory system based on the variable.

Abstract: A method of memory controller-independent memory mirroring includes providing a mirroring association between a first memory segment and a second memory segment that is independent of a memory controller. A memory buffer receives data from the memory controller that is directed to a first memory location in the first memory segment. The memory buffer writes the data, independent of the memory controller, to both the first memory segment and the second memory segment according to the mirroring association. The memory buffer receives a plurality of read commands from the memory controller that are directed to the first memory location in the first memory segment and, in response, reads data from an alternating one of the first memory segment and the second memory segment and stores both first data from the first memory segment and second data from the second memory segment.

Abstract: A method of selectively enabling error checking in an information handling system, including receiving information indicating that data associated with a first memory portion in a system memory should be subject to error checking during transmission between the memory controller and the system memory and indicating that data associated with a second memory portion in the system memory should be free of error checking during transmission between the memory controller and the system memory, receiving a memory access request directed to one of the first and second memory portions, transmitting data between the memory controller and the system memory in response to the memory access request, and selectively performing an error checking technique on the transmitted data based on the information.

Abstract: An apparatus including a first connector configured to fit into a first socket in a processing system, the first connector and first socket conforming to a first standard, a second socket configured to accept a memory module therein, the second socket and the memory module conforming to a second standard, a memory buffer module communicatively coupled to the first connector and the second socket, the memory buffer module configured to receive signals associated with the first standard from the first connector and output signals associated with the second standard to the second socket, and a virtualization module communicatively coupled to the memory buffer module, the first connector, and the second socket, the virtualization module configured to receive first initialization data associated with the second standard from the second socket and output second initialization data associated with the first standard to the processing system.

Abstract: In accordance with the present disclosure, a system and method for performing a system memory save in tiered or cached storage during transition to a decreased power state is disclosed. As disclosed herein, the system incorporating aspects of the present invention may include a flash or other nonvolatile memory such as a solid-state drive, volatile memory, and at least one alternate storage media. Upon transition to a decreased power state, at least some of the data in the solid-state drive, for example, may be transferred to the at least one alternate storage media. After the SSD data is transferred, data stored in volatile system memory, such as a system context, may be transferred to the SSD memory. With the system context saved in SSD memory, power to the volatile system memory may be turned off.

Abstract: Systems and methods for reducing problems and disadvantages associated with wear leveling in storage devices are disclosed. A method may include maintaining module usage data associated with each of a plurality of storage device modules communicatively coupled to a channel. The method may also include maintaining device usage data associated with each of the plurality of storage devices associated with the storage device module for each of the plurality of storage device modules. The method may additionally include determining a particular storage device module of the plurality of storage device modules to which to store data associated with a write request based at least on the module usage data. The method may further include determining a particular storage device of the particular storage device module to which to store data associated with a write request based at least on the device usage data associated with the particular storage device module.

Abstract: A memory error checking system includes a controller that is operable to transmit memory signals and error check signals. A first memory device coupler is coupled to the controller and operable to couple to a first memory device. The first memory device coupler is operable to transmit the memory signals from the controller to the first memory device. A first error check device coupler is coupled to the contoller and operable to couple to a first error check device that is separate from the first memory device. The first error check device coupler is operable to transmit the error check signals from the controller to the first error check device to be used to error check the memory signals transmitted to the first memory device.

Abstract: Systems and methods for reducing problems and disadvantages associated with power consumption in memory devices are disclosed. In accordance with one embodiment of the present disclosure, a method for improving performance and reducing power consumption in memory may include tracking whether individual units of a memory system are active or inactive. The method may also include placing inactive individual units of the memory system in a self-refresh mode, such that the inactive individual units self-refresh their contents. The method may further include placing active individual units of the memory system in a command-based refresh mode, such that the active individual units are refreshed in response to a received command to refresh their contents.

Abstract: Systems and methods for reducing problems and disadvantages associated with power consumption in memory devices are disclosed. A method for reducing power consumption in memory may include tracking, by an operating system executing on a processor, one or more logical units of a memory system that are in use. The method may also include setting, by the operating system, a variable indicating a portion of the memory system in use based on the logical units of the memory system in use. The method may additionally include refreshing one or more of the one or more logical units of the memory system based on the variable.

Abstract: A system and method for serial interface topologies is disclosed. A serial interface topology includes a replication device configured to receive control information from a controller interface. The replication device is configured to transmit two or more copies of substantially replicated control information to a device control interface. A data interface is configured to provide differential, point-to-point communication of data with the device controller interface.

Abstract: Systems and methods for reducing problems and disadvantages associated with wear leveling in storage devices are disclosed. A method may include maintaining module usage data associated with each of a plurality of storage device modules communicatively coupled to a channel. The method may also include maintaining device usage data associated with each of the plurality of storage devices associated with the storage device module for each of the plurality of storage device modules. The method may additionally include determining a particular storage device module of the plurality of storage device modules to which to store data associated with a write request based at least on the module usage data. The method may further include determining a particular storage device of the particular storage device module to which to store data associated with a write request based at least on the device usage data associated with the particular storage device module.

Abstract: A memory error checking system includes a controller that is operable to transmit memory signals and error check signals. A first memory device coupler is coupled to the controller and operable to couple to a first memory device. The first memory device coupler is operable to transmit the memory signals from the controller to the first memory device. A first error check device coupler is coupled to the controller and operable to couple to a first error check device that is separate from the first memory device. The first error check device coupler is operable to transmit the error check signals from the controller to the first error check device to be used to error check the memory signals transmitted to the first memory device.

Abstract: In a memory device to store information, the device includes a memory core to store information, a memory controller to control storage and retrieval of the information, and a regulator coupled to the memory controller and the memory core, wherein the regulator is operable to adjust an internal voltage to the memory core in response to commands from the memory controller.

Abstract: An information handling system includes support for dynamic power throttling. In one embodiment, an information handling system includes power level detection and power control modules. The power level detection module may monitor power consumption for the information handling system and may automatically transmit power level data to a power level manager, based on the monitored power consumption. The power control module may receive power control data from the power level manager. The power control module may also automatically adjust power consumption of the information handling system, in accordance with the power control data received from the power level manager. In another embodiment, an information handling system may include an interface and a power level manager. The power level manager may receive power information for computers via the interface, may automatically compute an adjusted power threshold setting, and may automatically transmit the adjusted power threshold setting to a computer.

Abstract: Information handling system errors are presented at a display with the information handling system graphics subsystem inoperative by communicating an identified error to the display through an auxiliary channel and generating a presentation of the error information with a microcontroller of the display. For example, errors determined by BIOS firmware running on a chipset are communicated through a DDC or I2C channel from the chipset to the display so that textual error messages are generated at the display without the use of the information handling system's graphic processor to generate an error message image.

Abstract: Processing components to manufacture information handling systems have build-to-order integrated circuits with plural selectively-enabled features set at the information handling system manufacture location. For instance, fuses integrated in the integrated circuits are selectively blown at the information handling system manufacture location to permanently disable features so that the processing components have a desired configuration. As another example, feature enable or disable states are programmed in flash incorporated in the integrated circuit, with the flash programmability subsequently disabled to permanently set the features so that the processing components have a desired configuration. Features are set with keys provided by the processing component manufacturer to track the information handling system manufacturer's use of the features.

Abstract: The present invention provides a configuration jumper that allows the main system board of an information handling system to be configured for a plurality of population options, including on-board PCI-E integrated circuits and PCI-E integrated circuits on expansion circuit boards that are connected to the main system board by an expansion slot connector. In one embodiment of the invention, the main system board comprises a first conductor and a second conductor that is selected from a plurality of second conductors that correspond to different circuit population options. The configuration jumper is operable to connect the first connector to the selected second conductor and to provide an appropriate capacitance to ensure that the signal path defined by the first conductor, the second conductor and the internal conductor of the jumper provide a combined AC coupling capacitance that complies with the AC coupling capacitor requirements of the PCI-E protocol.