Abstract: An active SAN discovery system and method responds to events occurring in SAN by automatically broadcasting for information related to the occurred events and updating the SAN topology according to the collected information.

Abstract: The present invention provides a system and method for facilitating a transaction using a secondary transaction number that is associated with a cardholder's primary account. The cardholder provides the secondary transaction number, often with limited-use conditions associated therewith, to a merchant to facilitate a more secure and confident transaction.

Abstract: The present invention provides a system and method for facilitating a transaction using a secondary transaction number that is associated with a cardholder's primary account. The cardholder provides the secondary transaction number, often with limited-use conditions associated therewith, to a merchant to facilitate a more secure and confident transaction.

Abstract: A test system includes a built-in self-test (BIST) circuit and a stress applicator for use in analyzing a memory array. The stress applicator applies a selective set of stress factors to the memory array, such as temperature and voltage conditions. The BIST circuit executes a test routine on the memory array to detect the presence of any faulty memory address locations that may arise under the prevailing stress condition. A full testing cycle involves iterative repetition of the functions performed by the stress applicator and BIST circuit, with variations in the stress factors across the testing iterations. An accumulator cumulatively stores the fault information generated by the BIST circuit during each testing iteration. Following completion of the testing cycle, a repair operation is performed by a built-in self-repair (BISR) circuit to remap the faulty memory address locations indicated by the accumulator to redundant memory address locations.

Abstract: The subject invention relates to systems and methods that facilitate motion between different coordinate systems in an industrial control environment. The systems and methods accept data in one coordinate system and transform the data to a different coordinate system. Suitable transformations include instructions that transform between Cartesian, pre-defined non-Cartesian, and user-defined non-Cartesian coordinate systems, including transformations between a non-Cartesian coordinate system to another non-Cartesian coordinate system. Such transformations can be programmed in essentially any industrial control language and can be seamlessly integrated with the control environment. The systems and methods can be utilized to generate a motion instruction that includes, among other information, source and target coordinate systems and the transformation between them.

Abstract: A test system includes a built-in self-test (BIST) circuit and a stress applicator for use in analyzing a memory array. The stress applicator applies a selective set of stress factors to the memory array, such as temperature and voltage conditions. The BIST circuit executes a test routine on the memory array to detect the presence of any faulty memory address locations that may arise under the prevailing stress condition. A full testing cycle involves iterative repetition of the functions performed by the stress applicator and BIST circuit, with variations in the stress factors across the testing iterations. An accumulator cumulatively stores the fault information generated by the BIST circuit during each testing iteration. Following completion of the testing cycle, a repair operation is performed by a built-in self-repair (BISR) circuit to remap the faulty memory address locations indicated by the accumulator to redundant memory address locations.

Abstract: A method, system and computer program product for communicating to a consumer one or more offers at a merchant communication device. Predefined offers are stored in a database. A portal selects one or more of the predefined offers, which are then communicated to the consumer through the merchant communication device. The consumer's response to the at least one offer is accepted and the transaction is completed accordingly.

Abstract: A method for testing semiconductor devices advantageously increases manufacturing yields. The method includes generating memory repair data for a wafer die by writing at least one predetermined digital bit pattern into a memory on the wafer die, reading the at least one predetermined digital bit pattern back out of the memory, comparing the at least one predetermined digital bit pattern read out from the memory against the at least one predetermined digital bit pattern written into the memory, and storing results of the comparison as the memory repair data. The writing and reading are performed a plurality of times, each time with a different voltage and clock frequency combination being applied to the wafer die. The memory repair data is programmed into the wafer die, and the wafer die is assembled into a packaged semiconductor device.

Abstract: An active SAN discovery system and method responds to events occurring in SAN by automatically broadcasting for information related to the occurred events and updating the SAN topology according to the collected information.

Abstract: The subject invention relates to systems and methods that facilitate motion between different coordinate systems in an industrial control environment. The systems and methods accept data in one coordinate system and transform the data to a different coordinate system. Suitable transformations include instructions that transform between Cartesian, pre-defined non-Cartesian, and user-defined non-Cartesian coordinate systems, including transformations between a non-Cartesian coordinate system to another non-Cartesian coordinate system. Such transformations can be programmed in essentially any industrial control language and can be seamlessly integrated with the control environment. The systems and methods can be utilized to generate a motion instruction that includes, among other information, source and target coordinate systems and the transformation between them.

Abstract: A battery cap device, “Acid Stripper”, to be used in the formation process of battery manufacturing. The cap's design is not applicable for use by the end user of the batteries. During the formation process, the batteries internally generate gasses which vent out from the top cover of the battery, carrying the acid mist with them. The release of this acid mist is an undesirable condition. The vented battery cap or “Acid Stripper” herein consists of a battery cap with gasket on which is welded and attached a static mixing tube. The static mixing tube has a double helix insert that removes the liquid acid and mist carried by the gasses, and drains it back into the battery. This substantially prevents any acid from escaping to the outside of the battery during the formation process. The prevention of the acid escape eliminates the damage to the floor, the environment, the equipment and the people breathing the air.

Abstract: A motion control system comprises control logic and a programming interface. The programming interface is configured to permit a user to specify a plurality of non-tangential path segments, and the control logic is configured to generate a plurality of additional connecting path segments substantially extending between and connecting the non-tangential path segments. The motion control system is configured to generate control signals to control operation of a plurality of motors to drive movement of a controlled element along a path defined by the non-tangential path segments and the additional connecting path segments.

Abstract: The present invention provides a system and method for facilitating a transaction using a secondary transaction number that is associated with a cardholder's primary account. The cardholder provides the secondary transaction number, often with limited-use conditions associated therewith, to a merchant to facilitate a more secure and confident transaction.

Abstract: The present invention provides a system and method for facilitating a transaction using a secondary transaction number that is associated with a cardholder's primary account. The cardholder provides the secondary transaction number, often with limited-use conditions associated therewith, to a merchant to facilitate a more secure and confident transaction.

Abstract: The present invention provides a system and method for facilitating a transaction using a secondary transaction number that is associated with a cardholder's primary account. The cardholder provides the secondary transaction number, often with limited-use conditions associated therewith, to a merchant to facilitate a more secure and confident transaction.

Abstract: A fast method and apparatus for built-in self-repair (BISR) of memory arrays is disclosed. In one embodiment, an integrated circuit includes a repair circuit coupled between the address decoder and the memory array. The address decoder receives memory addresses and asserts corresponding word lines. The memory array has default words associated with the word lines, but also includes extra words. By default, the repair circuit maps the word lines from the address decoder to the memory array word lines for the default words. However, the repair circuit includes at least one latch for each of the decoder word lines. When a latch is set, the repair circuit isolates the decoder word line from the default word and remaps the decoder word line to an extra word in the memory. The latches remain set while as long as power is applied, so that accesses to faulty memory words are automatically rerouted without any additional overhead relative to accesses to functional memory words.

Abstract: A memory device configured to detect changes in fault patterns is disclosed. In one embodiment, the memory device includes a memory array, a built-in self-test (BIST) unit, and a built-in self-repair (BISR) unit. The BIST unit runs test patterns on the memory array to identify faulty locations in the array. A comparator within the BIST or external to the BIST compares the actual output of the memory array to the expected output, and asserts an error signal whenever a mismatch occurs. The BISR unit intercepts addresses directed to the memory array, and operates on the addresses in three distinct phases. During a training phase, the BISR unit stores the intercepted addresses when the error signal is asserted. During the normal operation phase, the BISR unit compares all intercepted addresses to stored addresses and redirects a corresponding memory access if any intercepted address matches a stored address.

Abstract: A falling film of water is applied around the periphery of a fluid bed olefin polymerization reactor to cool the wall and reduce the temperature in the fluid bed near the inside surface of the wall. Cooling has the effect of reducing static in the reactor, which in turn ameliorates a sheeting problem and can enhance production by facilitating control of the relation of the reactor temperature and the dew point of recycled gas. The process may be used concurrently with a gas cooling and condensing recycle system wherein at least some of the condensed recycle gas is injected in the vicinity of the internal wall surface.

Abstract: A falling film of water is applied around the periphery of a fluid bed olefin polymerization reactor to cool the wall and reduce the temperature in the fluid bed near the inside surface of the wall. Cooling has the effect of reducing static in the reactor, which in turn ameliorates a sheeting problem and can enhance production by facilitating control of the relation of the reactor temperature and the dew point of recycled gas. The process may be used concurrently with a gas cooling and condensing recycle system wherein at least some of the condensed recycle gas is injected in the vicinity of the internal wall surface.

Abstract: An integrated circuit device is disclosed having a BIST Uinit with recolfiLgurable data retention testing for a memory array. In one embodiment, the integrated circuit device includes a memory array, a BIST unit, an externally-programmable pause count register, and a pause counter. The BIST unit is configured to apply a test pattern of memory accesses to the memory array. The test pattern preferably includes a first phase for writing data values to the memory array, a second phase for stressing the memory array, and a third phase for verifying the data values after the array has been stressed. The length of the second phase is determined by the count stored in the externally-programmable register. The count may be loaded into the pause counter by the BIST prior to the second phase. In the second phase, the BIST unit asserts a pause signal which causes the pause counter to suppress the clock signal to the BIST unit during the second phase, thereby suspending the BIST unit's activity.