Abstract: In one embodiment, a circuit includes a first mixer cell and a second mixer cell that each have respectively a first cell input, a second cell input, and a cell output. The circuit includes a first circuit input configured to receive a first input signal having a first phase. The first circuit input is connected to the first cell input of the first mixer cell and the second cell input of the second mixer cell. The circuit includes a second circuit input configured to receive a second input signal having a second phase separated from the first phase by a nominal value. The second circuit input is connected to the second cell input of the first mixer cell and the first cell input of the second mixer cell.

Abstract: In one embodiment, a circuit includes a first circuit input for receiving a first input signal having a first phase; a second circuit input for receiving a second input signal having a second phase; a circuit output for outputting a circuit output signal; a first mixer cell comprising a first mixer cell input, a second mixer cell input, and a first mixer cell output; and a second mixer cell comprising a third mixer cell input, a fourth mixer cell input, and a second mixer cell output. The first circuit input is connected to the first and second mixer cell inputs, the second circuit input is connected to the second and fourth mixer cell inputs, and the first and second mixer cell outputs are combined to provide the circuit output. The current of the circuit output signal is proportional to a phase offset between the first and second phases.

Abstract: In one embodiment, a method includes receiving input data bits over data channels; receiving deskew channel bits constituting frames that each comprise ones of the input data bits; determining frame boundaries; mapping each of the input data bits in each of the frames to one of the data channels; for each set of the frames, comparing the input data bits in the set with the input data bits in the corresponding input data words; determining relative delays among the data channels and the deskew channel; when non-zero delays are determined, rearranging the input data bits to reduce the delays; and when it is determined that one or more of the data channels have a delay of greater than a predetermined number of data-channel clock periods relative to a particular data channel, delaying input data bits in the particular data channel by an additional number of input data bits.

Abstract: In one embodiment, a method includes receiving a data signal comprising a plurality of bits. The method further includes generating a clock signal. A plurality of samples is acquired from the data signal at a sampling rate determined by the clock signal and it is determined whether a transition point from a first bit in the plurality of bits to a second bit in the plurality of bits occurs within the plurality of samples. If it is determined that the transition point occurs within the plurality of samples, a state machine comprising a plurality of states transitions from a first state to a second state. If the second state indicates a non-zero amount of phase displacement between the clock signal and the data signal, the clock signal is adjusted to correlate with the data signal.

Abstract: In one embodiment, a method includes, in response to assertion of a write-enable signal at a memory array that comprises a plurality of words, sequentially and at a first clock frequency writing data to the memory array starting at a beginning of the memory array until the memory array is full. The method includes, independent of the writing of data to the memory array, asynchronously and at a second clock frequency that is slower than the first clock frequency reading data from the memory array based on read addresses received at the memory array.

Abstract: In one embodiment, a circuit includes a first circuit input for receiving a first reference signal having a first phase; a second circuit input for receiving a second reference signal having a second phase; a third circuit input for receiving a target phase signal; a circuit output for outputting an output signal; a first multiplying mixer cell (MMC) comprising a first MMC input, a second MMC input, and a first MMC output; a second MMC comprising a third MMC input, a fourth MMC input, and a second MMC output.

Abstract: In one embodiment, a method for computing jitter in a clock tree includes dividing a clock tree into a plurality of stages and computing jitter in one or more of the stages according to a model of at least a portion of a circuit associated with the clock tree. The model includes a representation of each source of jitter in the circuit. The method also includes, to compute jitter associated with a path or a pair of paths in the clock tree, statistically combining the jitter in each of the stages of the path or the pair of paths in the clock tree with each other. In one embodiment, to efficiently compute jitter and to achieve zero clock skew, a method synthesizes a symmetrical clock tree of a circuit in which corresponding stages in all paths from a root of the clock tree to sinks of the clock tree exhibit approximate electrical equivalence to each other.

Abstract: In one embodiment, a method includes accessing a description of a chip including multiple sequential elements and a clock mesh, information for modeling the sequential elements and interconnections, and a set of parameters of the clock mesh. The method also includes, using the description of the chip, the information for modeling the sequential elements and interconnections, and the set of parameters of the clock mesh, determining multiple original window locations covering the clock mesh. Each window location includes one or more of the sequential elements on the chip.

Abstract: In one embodiment, a method includes accessing a description of a chip including multiple sequential elements and a clock mesh, information for modeling the sequential elements and interconnections, and a set of parameters of the clock mesh. The method also includes, using the description of the chip, the information for modeling the sequential elements and interconnections, and the set of parameters of the clock mesh, determining multiple window locations covering the clock mesh. Each window location includes one or more of the sequential elements on the chip. The method also includes, for each window location, generating a mesh simulation model including a detailed model inside the window location and an approximate model outside the window location, simulating the mesh simulation model, and measuring clock timing for the sequential elements in the window location based on the mesh simulation model.

Abstract: In one embodiment, a method includes receiving first and second input streams comprising first and second input data bits, respectively. The method includes generating first and second recovered clocks based on the first and second input streams, respectively. The method includes retiming and demultiplexing the first and second input data bits to generate n first recovered streams and n second recovered streams, respectively, each comprising first and second recovered data bits, respectively. The method further includes determining a phase difference between the first and second recovered clocks; aligning the first recovered data bits with the second recovered data bits based at least in part on a value of n and the phase difference; combining the first and second recovered data bits to generate an output stream; and retiming the first and second recovered data bits in the output stream based on either the first or second recovered clock.

Abstract: In one embodiment, a circuit includes a first circuit input for receiving a first reference signal having a first phase; a second circuit input for receiving a second reference signal having a second phase; a third circuit input for receiving a target phase signal; a circuit output for outputting an output signal; a first multiplying mixer cell (MMC) comprising a first MMC input, a second MMC input, and a first MMC output; a second MMC comprising a third MMC input, a fourth MMC input, and a second MMC output.

Abstract: In one embodiment, a circuit includes a voltage-controlled oscillator (VCO) configured to generate k first clock signals that each have a first phase based on a charge-pump control voltage signal; one or more phase interpolators (PIs) configured to receive the k first clock signals and one or more first feedback controls signals and generate m second clock signals that each have a second phase based on the k first clock signals and the one or more first feedback control signals; a first phase detector (PD) configured to receive the m second clock signals and generate the one or more first feedback control signals based on the m second clock signals; a second PD configured to generate one or more second feedback control signals based on the m second clock signals; and a charge pump configured to output the charge-pump control voltage signal based on the second feedback control signals.

Abstract: In one embodiment, a circuit includes a first circuit input for receiving a first input signal having a first phase; a second circuit input for receiving a second input signal having a second phase; a circuit output for outputting a circuit output signal; a first mixer cell comprising a first mixer cell input, a second mixer cell input, and a first mixer cell output; and a second mixer cell comprising a third mixer cell input, a fourth mixer cell input, and a second mixer cell output. The first circuit input is connected to the first and second mixer cell inputs, the second circuit input is connected to the second and fourth mixer cell inputs, and the first and second mixer cell outputs are combined to provide the circuit output. The current of the circuit output signal is proportional to a phase offset between the first and second phases.

Abstract: In one embodiment, a method includes accessing a reference clock having a reference clock frequency and reference clock phase; generating an output clock having an output clock phase and output clock frequency that is a function of an analog control voltage setting and a frequency gain curve; fixing the analog control voltage setting to a predetermined voltage; selecting one of the frequency gain curves within a predetermined frequency range of the reference clock frequency at the analog control voltage setting; adjusting the analog control voltage setting to adjust the output clock frequency to be within another predetermined frequency range of the reference clock frequency; and adjusting the output clock phase to be within a predetermined phase range of an input data phase of the input data stream.

Abstract: The disaster recovery techniques, for presentment of a company's bills, statements or the like, provide electronic document presentment in the event of a disaster that impacts the company's print mail delivery operation or other existing mailing system(s). Files containing electronic documents are received, from a system associated with the print mail delivery operation, and the documents are stored in a database. Preferably, the systems use the company's existing data files. The files may be converted to a format compatible with one or more electronic delivery methodologies, if necessary. The disaster recovery systems present notice and/or data from the documents to the company's customers electronically, for example as e-mail (notice or message containing some or all of the document data), as a document attachment to an e-mail, via a web site, and possibly via telephone voice announcement.

Abstract: In one embodiment, a method includes receiving input data bits at a collective data rate, the input data bits being grouped into a plurality of input data words, the input data bits of each of the input data words being received from n parallel input-data-bit streams, each of the n parallel input-data-bit streams having a stream data rate that is 1/n of the collective data rate, each of the input data words comprising n consecutive ones of the input data bits; selecting particular input data bits; and generating a k-bit deskew channel with the selected input data bits, the deskew channel comprising a number of frames, each of the frames comprising x input data bits from one or more input data words and one or more framing bits. In another embodiment, a method includes using such a deskew channel to determine relative delays between data channels and the deskew channel.

Abstract: In one embodiment, a method is described that includes receiving a first clock signal and a second clock signal; dividing the first clock signal by a value of n to generate a divided first clock signal; sampling the frequency detector the divided first clock signal with the second clock signal to generate a plurality of samples; generating a first adjustment signal if more than a predetermined number of consecutive samples in a set of consecutive samples have identical logical values; and generating a second adjustment signal if less than the predetermined number of consecutive samples in the set of consecutive samples have identical logical values.

Abstract: A system and method for constructing a clock tree based on replica stages is described. The system and method may comprise determining a size of an input buffer for driving a load capacitance of the output buffer based on a fanout, determining a wire width and a wire length based on the size of the output buffer, the fanout and a replica stage mathematical model, and connecting the output buffer and the corresponding input buffer to a conductor routed on one or more predetermined metal layers and having the wire length and the wire width. The conductor is placed within ground shields having a fixed width.

Abstract: In particular embodiments, an apparatus includes a first transistor connected at the gate to a first input signal voltage and a second transistor connected at the gate to a second input signal voltage. The apparatus further includes a deactivation element coupled to the transistors, the deactivation element being operable to deactivate the first and second transistors by selectively transmitting a deactivation current to a first terminal of the first transistor and a second terminal of the second transistor thereby raising a voltage on the first and second terminals to a value large enough to deactivate the first and second transistors. In particular embodiments, activating the first or second transistor transmits a signal from the apparatus and deactivating the first and second transistors prevents the signal from being transmitted from the apparatus.

Abstract: Disclosed are multiphase oscillators comprising a plurality of delay stages serially coupled in a loop by a plurality of nodes, with the loop being folded to provide two concentric rings of delay stages with equal numbers of allocated nodes. A second plurality of negative-resistance elements are provided, each element having a first output coupled to a node on the first concentric ring and a second output coupled to a node on the second concentric ring. Each such output switches between first and second voltage levels, and provides a negative resistance to a signal coupled to it during at least a portion of the transition between voltage levels. The outputs of an element switch to opposite voltage levels. With this construction, a high-voltage pulse propagates around the loop of delay stages, with a low-voltage pulse propagating behind it. Also disclosed are circuits to control the direction of pulse propagation.