Patents by Inventor William W. Walker
William W. Walker has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20090037762Abstract: The disaster recovery techniques, for presentment of a company's bills, statements or the like, provide electronic document presentment in the event of a disaster that impacts the company's print mail delivery operation or other existing mailing system(s). Files containing electronic documents are received, from a system associated with the print mail delivery operation, and the documents are stored in a database. Preferably, the systems use the company's existing data files. The files may be converted to a format compatible with one or more electronic delivery methodologies, if necessary. The disaster recovery systems present notice and/or data from the documents to the company's customers electronically, for example as e-mail (notice or message containing some or all of the document data), as a document attachment to an e-mail, via a web site, and possibly via telephone voice announcement.Type: ApplicationFiled: January 3, 2003Publication date: February 5, 2009Inventors: Francesco Gozzo, Emmett M. Perry,, JR., William W. Walker, Michael J. Maselli, James N. Sutton,, JR.
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Publication number: 20080192873Abstract: In one embodiment, a method includes receiving a data signal comprising a plurality of bits. The method further includes generating a clock signal. A plurality of samples is acquired from the data signal at a sampling rate determined by the clock signal and it is determined whether a transition point from a first bit in the plurality of bits to a second bit in the plurality of bits occurs within the plurality of samples. If it is determined that the transition point occurs within the plurality of samples, a state machine comprising a plurality of states transitions from a first state to a second state. If the second state indicates a non-zero amount of phase displacement between the clock signal and the data signal, the clock signal is adjusted to correlate with the data signal.Type: ApplicationFiled: January 30, 2008Publication date: August 14, 2008Applicant: Fujitsu LimitedInventors: Hirotaka Tamura, Nikola Nedovic, William W. Walker
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Publication number: 20080191770Abstract: In particular embodiments, an apparatus includes a first transistor connected at the gate to a first input signal voltage and a second transistor connected at the gate to a second input signal voltage. The apparatus further includes a deactivation element coupled to the transistors, the deactivation element being operable to deactivate the first and second transistors by selectively transmitting a deactivation current to a first terminal of the first transistor and a second terminal of the second transistor thereby raising a voltage on the first and second terminals to a value large enough to deactivate the first and second transistors. In particular embodiments, activating the first or second transistor transmits a signal from the apparatus and deactivating the first and second transistors prevents the signal from being transmitted from the apparatus.Type: ApplicationFiled: December 19, 2007Publication date: August 14, 2008Applicant: Fujitsu LimitedInventors: Nikola Nedovic, William W. Walker
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Patent number: 7405593Abstract: Disclosed are on-chip global electrical signaling systems and methods employing differential current-mode sensing having reduced delay and energy dissipation compared to conventional inverter repeaters. The present inventions can be used for point-to-point connections as well as N-to-1 connections.Type: GrantFiled: November 1, 2005Date of Patent: July 29, 2008Assignee: Fujitsu LimitedInventors: Nestor Tzartzanis, William W. Walker
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Patent number: 7307483Abstract: Disclosed are multiphase oscillators comprising a plurality of delay stages serially coupled in a loop by a plurality of nodes, with the loop being folded to provide two concentric rings of delay stages with equal numbers of allocated nodes. A second plurality of negative-resistance elements are provided, each element having a first output coupled to a node on the first concentric ring and a second output coupled to a node on the second concentric ring. Each such output switches between first and second voltage levels, and provides a negative resistance to a signal coupled to it during at least a portion of the transition between voltage levels. The outputs of an element switch to opposite voltage levels. With this construction, a high-voltage pulse propagates around the loop of delay stages, with a low-voltage pulse propagating behind it. Also disclosed are circuits to control the direction of pulse propagation.Type: GrantFiled: February 3, 2006Date of Patent: December 11, 2007Assignee: Fujitsu LimitedInventors: Nestor Tzartzanis, William W. Walker
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Patent number: 7256621Abstract: Disclosed are keeper circuits for electronic circuits that selectively maintain the voltage level of an intermediate circuit node at a desired level. In one exemplary embodiment, a keeper transistor either provides current or drains current from the intermediate node to maintain the desired voltage level in response to a signal to do so. The keeper circuit works against a leakage current that either drains current from the node or supplies current to the node. A current-setting transistor is coupled in series with the keeper transistor to set the maximum current through the keeper circuit to a value that is related to this leakage current, preferably tracking the leakage current. With this construction, the current-setting transistor is able to track variations in the leakage current caused by variations in the manufacturing process, and thereby provide dynamic leakage compensation.Type: GrantFiled: March 25, 2005Date of Patent: August 14, 2007Assignee: Fujitsu LimitedInventors: Yolin Lih, William W. Walker
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Patent number: 7075842Abstract: Disclosed is a memory architecture where current sense amplifiers are used instead of voltage sense amplifiers, and where the memory cells normally disposed along a single bit line are divided between two half bit lines. Each half bit line is coupled to a respective input of the current sense amplifier. When one of the memory cells is selected for reading, it couples a current related to its stored data state to the half bit line that it is coupled to. During this operation, a reference current is generated on the other half bit line. Also disclosed are novel current sense amplifiers.Type: GrantFiled: February 13, 2004Date of Patent: July 11, 2006Assignee: Fujitsu LimitedInventors: Nestor Tzartzanis, William W. Walker
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Patent number: 7027345Abstract: Techniques, including a system and method, are disclosed for conditionally pre-charging a memory circuit, for example a flip-flop, and thus reducing power consumption. In an embodiment a method for reducing power consumption in a memory circuit, including, a pre-charged stage coupled to an evaluation stage by at least an internal node, is provided. The method includes setting an input of the pre-charged stage to a first high logic level. Next, responsive to the setting of the input, the internal node is set to a low logic level within a first transparency window. Then responsive to the setting of the internal node, the evaluation stage changes the output of the evaluation stage to a second high logic level within the first transparency window. Lastly, when the input remains at the first high-logic level, the internal node is maintained at the low logic level through at least a second transparency window.Type: GrantFiled: January 11, 2002Date of Patent: April 11, 2006Assignee: Fujitsu LimitedInventors: Nikola Nedovic, Vojin G. Oklobd{hacek over (z)}ija, William W. Walker
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Patent number: 6842046Abstract: A system and method, for converting a voltage input from a low voltage source to a voltage output at a high voltage source using a domino logic circuit design. An embodiment provides a low to high voltage conversion system. The system includes: a pull-up transistor coupled to a high voltage source for charging a node, when a precharge signal is received; a low voltage source used for setting an input voltage; a pull-down network for discharging the node depending, at least in part, on the input voltage; and an output voltage determined from the node.Type: GrantFiled: January 31, 2002Date of Patent: January 11, 2005Assignee: Fujitsu LimitedInventors: Nestor Tzartzanis, William W. Walker
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Patent number: 6778466Abstract: An improved multi-port memory cell circuit which has a smaller number of write lines and/or transistors than conventional multi-port memory cells, and hence occupies a smaller area, is provided. The reduced area memory cell circuit includes: word lines associated with each bit line of a set of bit lines; a first word line for selecting a subset of the set of bit lines; a second word line for selecting a bit line of the subset of bit lines; and a memory cell for storing a bit value on the selected bit line.Type: GrantFiled: April 11, 2002Date of Patent: August 17, 2004Assignee: Fujitsu LimitedInventor: William W. Walker
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Patent number: 6753715Abstract: A Symmetric Pulse Generator Flip-Flop (SPG-FF). The flip-flop comprises two pulse generator stages that each respond to one particular transition of an input clock signal. Thus, the flip-flop is triggered on both the rising and falling edge of the clock signal to capture an input data signal. The outputs of the generator stages are combined to form a flip-flop output.Type: GrantFiled: September 20, 2002Date of Patent: June 22, 2004Assignee: Fujitsu LimitedInventors: Volin G. Oklobdzija, William W. Walker, Nikola M. Nedovic
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Publication number: 20040057313Abstract: A Symmetric Pulse Generator Flip-Flop (SPG-FF). The flip-flop comprises two pulse generator stages that each respond to one particular transition of an input clock signal. Thus, the flip-flop is triggered on both the rising and falling edge of the clock signal to capture an input data signal. The outputs of the generator stages are combined to form a flip-flop output.Type: ApplicationFiled: September 20, 2002Publication date: March 25, 2004Inventors: Volin G. Oklobdzija, William W. Walker, Nikola M. Nedovic
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Patent number: 6693459Abstract: The present invention provides techniques, including a system and method, for improving speed in a flip-flop, having a pre-charged stage coupled to an evaluation stage. In one exemplary embodiment delay is reduced by using a conditional rather than an unconditional keeper, where the conditional keeper has the function of a keeper only under certain conditions. In some embodiments there is a conditional keeper in either the pre-charged stage or the evaluation stage or both stages. Another embodiment provides for the combining of the evaluation stage with one or more external logic functions.Type: GrantFiled: January 11, 2002Date of Patent: February 17, 2004Assignee: Fujitsu LimitedInventors: Nikola Nedovic, Vojin G. Oklobd{haeck over (z)}ija, William W. Walker
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Patent number: 6646487Abstract: The invention relates generally to the field of electronic circuit design, and in particular to techniques for reducing hazards in a digital logic circuit, for example, a digital logic flip-flop circuit. In an embodiment of the present invention a method for reducing hazards in a flip-flop, including, a pre-charged stage coupled to an evaluation stage by at least an internal node, is provided. First, the pre-charged stage sets the internal node based on a data input. The evaluation stage is prevented from evaluating the internal node for a predetermined time period. After the predetermined time period, the internal node is evaluated by the evaluation stage to determine an output of the flip-flop.Type: GrantFiled: January 11, 2002Date of Patent: November 11, 2003Assignee: Fujitsu LimitedInventors: Nikola Nedovic, Vojin G. Oklobd{haeck over (z)}ija, William W. Walker
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Publication number: 20030198094Abstract: An improved multi-port memory cell circuit which has a smaller number of write lines and/or transistors than conventional multi-port memory cells, and hence occupies a smaller area, is provided. The reduced area memory cell circuit includes: word lines associated with each bit line of a set of bit lines; a first word line for selecting a subset of the set of bit lines; a second word line for selecting a bit line of the subset of bit lines; and a memory cell for storing a bit value on the selected bit line.Type: ApplicationFiled: April 11, 2002Publication date: October 23, 2003Applicant: Fujitsu LimitedInventor: William W. Walker
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Publication number: 20030141899Abstract: A system and method, for converting a voltage input from a low voltage source to a voltage output at a high voltage source using a domino logic circuit design. An embodiment provides a low to high voltage conversion system. The system includes: a pull-up transistor coupled to a high voltage source for charging a node, when a precharge signal is received; a low voltage source used for setting an input voltage; a pull-down network for discharging the node depending, at least in part, on the input voltage; and an output voltage determined from the node.Type: ApplicationFiled: January 31, 2002Publication date: July 31, 2003Applicant: Fujitsu LimitedInventors: Nestor Tzartzanis, William W. Walker
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Publication number: 20030062940Abstract: The invention relates generally to the field of electronic circuit design, and in particular to techniques for reducing hazards in a digital logic circuit, for example, a digital logic flip-flop circuit. In an embodiment of the present invention a method for reducing hazards in a flip-flop, including, a pre-charged stage coupled to an evaluation stage by at least an internal node, is provided. First, the pre-charged stage sets the internal node based on a data input. The evaluation stage is prevented from evaluating the internal node for a predetermined time period. After the predetermined time period, the internal node is evaluated by the evaluation stage to determine an output of the flip-flop.Type: ApplicationFiled: January 11, 2002Publication date: April 3, 2003Applicant: Fujitsu LimitedInventors: Nikola Nedovic, Vojin G. Oklobdzija, William W. Walker
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Publication number: 20030062925Abstract: The present invention provides techniques, including a system and method, for improving speed in a flip-flop, having a pre-charged stage coupled to an evaluation stage. In one exemplary embodiment delay is reduced by using a conditional rather than an unconditional keeper, where the conditional keeper has the function of a keeper only under certain conditions. In some embodiments there is a conditional keeper in either the pre-charged stage or the evaluation stage or both stages. Another embodiment provides for the combining of the evaluation stage with one or more external logic functions.Type: ApplicationFiled: January 11, 2002Publication date: April 3, 2003Applicant: Fujitsu LimitedInventors: Nikola Nedovic, Vojin G. Oklobdzija, William W. Walker
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Publication number: 20030056129Abstract: Techniques, including a system and method, are disclosed for conditionally pre-charging a memory circuit, for example a flip-flop, and thus reducing power consumption. In an embodiment a method for reducing power consumption in a memory circuit, including, a pre-charged stage coupled to an evaluation stage by at least an internal node, is provided. The method includes setting an input of the pre-charged stage to a first high logic level. Next, responsive to the setting of the input, the internal node is set to a low logic level within a first transparency window. Then responsive to the setting of the internal node, the evaluation stage changes the output of the evaluation stage to a second high logic level within the first transparency window. Lastly, when the input remains at the first high-logic level, the internal node is maintained at the low logic level through at least a second transparency window.Type: ApplicationFiled: January 11, 2002Publication date: March 20, 2003Applicant: Fujitsu LimitedInventors: Nikola Nedovic, Vojin G. Oklobdzija, William W. Walker
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Patent number: 5987641Abstract: A wrist pad is provided including a flexible removable wrap with a top extent and a bottom extent. At least one sleeve is mounted on the bottom extent of the wrap. A rigid element includes at least one portion defining a periphery of a cylinder and a sphere. Such rigid element is removably situated within the sleeve during use.Type: GrantFiled: February 5, 1998Date of Patent: November 23, 1999Inventor: William W. Walker