Patents by Inventor William Y. Chen

William Y. Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6631465
    Abstract: A method and apparatus that provides instruction re-alignment using a branch on a falsehood of a qualifying predicate. A complementary predicate related to a qualifying predicate is determined to be available. Instructions are re-aligned using a branch on a falsehood of the qualifying predicate if the complementary predicate is not available. Thus, a complementary predicate does not have to be generated to re-align instructions if no complementary predicate is available for the qualifying predicate.
    Type: Grant
    Filed: June 30, 2000
    Date of Patent: October 7, 2003
    Assignee: Intel Corporation
    Inventors: William Y. Chen, Dong-Yuan Chen
  • Patent number: 6505345
    Abstract: An optimization process is disclosed. The process first finds a parallel compare sequence in a program flow, for example using a flow graph. The guarding predicate (gp) is obtained for the compares. If a new dominating predicate (dp) can be found, the process proceeds to determining if compares for the dp generate the correct or needed initial value for the gp. If there are free result slots available, the proper compares are generated and folded into the initialization. If no free slots are available, it is determined if there is a use of a gp between the dp and gp. If not, the dp is renamed to gp, and the proper compares are generated and folded into the initialization. If there is such a use, the guarding predicate of the compares is found and the process reiterates until it ends with the failure to find a new dominating predicate dp.
    Type: Grant
    Filed: January 18, 2000
    Date of Patent: January 7, 2003
    Assignee: Intel Corporation
    Inventors: William Y. Chen, Dong-Yuan Chen
  • Patent number: 6351849
    Abstract: A method for compiling comprising receiving a source program having a number of memory operation blocks that are mutually exclusive. Each of the memory operation blocks have a memory operation, such that the memory operation in each block is associated with a different memory address. Additionally, an executable program is generated based on the source program. The executable program includes an executable program section for each memory operation block of the source program such that each executable program section utilizes a same number of registers for each memory operation within each memory operation block.
    Type: Grant
    Filed: May 21, 1999
    Date of Patent: February 26, 2002
    Assignee: Intel Corporation
    Inventor: William Y. Chen