Patents by Inventor Williams A. Stevens

Williams A. Stevens has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180326635
    Abstract: An apparatus and method for actuating a valve stem between an open position and a closed position and for taking one or more valve gated nozzle out of service is disclosed. The hot runner includes a valve gated nozzle having a valve stem, the valve stem coupled to a piston that is held against an actuation plate via pressurized air. When a valve stem becomes stuck in a gate of the hot runner, the actuation plate can continue to move while the piston remains stationary. The valve stem may also be protected from an over force situation such as if the valve stem encounters an obstruction as the actuation plate is moving toward the closed position.
    Type: Application
    Filed: November 14, 2016
    Publication date: November 15, 2018
    Inventors: Stephen Daniel FERENC, William Steven KEIR, Brandon Douglas WHITE
  • Publication number: 20180235374
    Abstract: An orthopedic cushioning device and system which includes a base cushion(s) and a plurality of smaller, modular cushion elements that may be changeably attached and arranged without tools or mechanical control systems onto the base cushion(s) and onto other cushion elements to form a custom surface topography. This cushioning system is a fully portable, lightweight support solution for the comfort of all people and especially for those with special orthopedic requirements and other physical problems. The system is adaptable to a wide variety human body sizes, shapes and forms. It may be used as an overlay on existing human support systems like chairs, wheelchairs, beds and vehicle seating. User reconfigurable, it does not require any external or internal power sources. The cushion elements may be methodically arranged over time to affect change in the relationship between the bones and their related connecting tissues, tendons, cartilage and ligaments of the user.
    Type: Application
    Filed: February 17, 2017
    Publication date: August 23, 2018
    Inventor: William Steven Kroll
  • Publication number: 20180183581
    Abstract: Various embodiments for providing datalink security in a datalink between a first hardware device (e.g., a system-on-a-chip (SoC) device) and a second hardware device (e.g., an encrypted storage device) are described. Various embodiments using differing types of keys and setups are described and claimed.
    Type: Application
    Filed: December 28, 2016
    Publication date: June 28, 2018
    Applicant: INTEL CORPORATION
    Inventors: REOUVEN ELBAZ, DANIEL NEMIROFF, WILLIAM STEVENS, JR.
  • Patent number: 9895829
    Abstract: Disclosed herein, amongst other things, is a post-mold system (100, 200, 300, 400, 500) for conditioning a molded article (130). The post-mold system comprises a retrieval device (110, 210, 310, 410, 510) having a receptacle (112, 212, 312, 412, 512) that is configured to retrieve the molded article (130) from a mold (132) and a conditioning device (120, 320, 420, 520). The receptacle (112, 212, 312, 412, 512) is configured to be selectively transferable between the retrieval device (110, 210, 310, 410, 510) and the conditioning device (120, 320, 420, 520). The conditioning device (120, 320, 420, 520) includes a first thermal regulator (140, 240, 440) that is configured to thermally regulate the receptacle (112, 212, 312, 412, 512) when connected thereto.
    Type: Grant
    Filed: October 17, 2012
    Date of Patent: February 20, 2018
    Assignee: HUSKY INJECTION MOLDING SYSTEMS LTD.
    Inventors: William Steven Keir, Allan King Leung Lee, Darrin Albert MacLeod, Peter Yankov, Raymond Weiping Zhang
  • Publication number: 20180004979
    Abstract: A system-on-chip (SoC) includes a host CPU on a CPU fabric, the host CPU including multiple processor cores, each associated with multiple security attributes. The SoC includes a secure asset on a network-on-chip and a security co-processor. The security co-processor includes circuitry to detect requests from the processor cores targeting the secure asset and security function processing requests, to determine, based on associated security attributes, whether the core or function is authorized to access the secure asset, to allow the request to be issued, if the core or function is so authorized, and to prevent its issuance, if not. The determination may be dependent on a signal from the CPU fabric indicating whether the host CPU can modify its security attributes or they are locked down. The security co-processor may have the highest security level and may be the only master on the SoC that can access the secure asset.
    Type: Application
    Filed: July 1, 2016
    Publication date: January 4, 2018
    Inventors: Jose S. Niell, Gautham N. Chinya, Khee Wooi Lee, William A. Stevens, JR., Josh Triplett
  • Publication number: 20170364689
    Abstract: Technologies for securely binding a manifest to a platform include a computing device having a security engine and a field-programmable fuse. The computing device receives a platform manifest indicative of a hardware configuration of the computing device and a manifest hash. The security engine of the computing device blows a bit of a field programmable fuse and then stores the manifest hash and a counter value of the field-programmable fuse in integrity-protected non-volatile storage. In response to a platform reset, the security engine verifies the stored manifest hash and counter value and then determines whether the stored counter value matches the field-programmable fuse. If verified and current, trusted software may calculate a hash of the platform manifest and compare the calculated hash to the stored manifest hash. If matching, the platform manifest may be used to discover platform hardware. Other embodiments are described and claimed.
    Type: Application
    Filed: June 20, 2017
    Publication date: December 21, 2017
    Inventors: Pradeep M. Pappachan, Reshma Lal, Siddhartha Chhabra, Gideon Gerzon, Baruch Chaikin, Bin Xing, William A. Stevens, JR.
  • Publication number: 20170321109
    Abstract: An acid corrosion inhibitor is provided that is compatible with viscoelastic surfactants and useful for enhancing the production of hydrocarbon bearing formations. The viscoelastic surfactant can used in fracturing of subterranean formations penetrated by an oil or gas well or in connection with acidizing or other treatment processes. The acid corrosion inhibitor can include a viscoelastic surfactant and an active inhibition compound which can comprise a reaction product of thiourea, paraformaldehyde and acetophenone, or amines (linear or cyclic), amine quaternaries (linear or cyclic) or combinations or mixtures thereof.
    Type: Application
    Filed: May 9, 2017
    Publication date: November 9, 2017
    Applicant: BAKER HUGHES, A GE COMPANY, LLC
    Inventors: JINGSHE SONG, MICHAEL L. WALKER, HAFID J. HERNANDEZ, WILLIAM STEVENS
  • Publication number: 20170269837
    Abstract: Provided are a system, memory controller, and method for using counters and a table to protect data in a storage device. Upon initiating operations to modify a file in the storage device, a storage write counter is incremented in response to initiating the operations to modify the file. In response to incrementing the storage write counter, write table operations are initiated including setting a table write counter to a storage write counter and setting a table commit counter to the storage commit counter plus a value. The operation to modify the file in response to completing the write table operations. The system commit counter is incremented by the value in response to completing the operation to modify the file.
    Type: Application
    Filed: April 4, 2017
    Publication date: September 21, 2017
    Inventors: William A. STEVENS, JR., Nitin V. SARANGDHAR
  • Publication number: 20170161302
    Abstract: System and method for damage avoidance in an excavation area include: receiving an excavation area and an excavation depth; accessing a database of a plurality of utility assets to identify a buried utility asset within the excavation area and the excavation depth; retrieving information from the database for the identified buried utility asset; fusing the buffer zone associated with the buried utility asset and the depth of the buried utility asset to obtain a latitude buffer zone for the buried utility asset; comparing the latitude buffer zone for the buried utility asset and the excavation depth; identifying a party responsible for the buried utility asset; and automatically transmitting an electronic notification to the party responsible for the buried utility asset.
    Type: Application
    Filed: February 16, 2017
    Publication date: June 8, 2017
    Inventors: Nelson Page Tucker, Daniel Edward Colby, Peter James Lynch Forster, William Steven Slusarenko
  • Publication number: 20170112284
    Abstract: A method of protecting a cabinet includes the positioning of a liner on a bottom wall of a cabinet. The cabinet has a top wall and a perimeter wall that is attached to and extends between the top and bottom walls. The perimeter wall has a front side is open. At least one door is mounted on the perimeter wall to selectively open or close the front side. The liner includes a lower wall and a peripheral wall that is attached to and extends upwardly from the lower wall.
    Type: Application
    Filed: October 23, 2015
    Publication date: April 27, 2017
    Inventors: William Stevens, JR., Phyllis Stevens
  • Patent number: 9626119
    Abstract: Provided are a system, memory controller, and method for using counters and a table to protect data in a storage device. Upon initiating operations to modify a file in the storage device, a storage write counter is incremented in response to initiating the operations to modify the file. In response to incrementing the storage write counter, write table operations are initiated including setting a table write counter to a storage write counter and setting a table commit counter to the storage commit counter plus a value. The operation to modify the file in response to completing the write table operations. The system commit counter is incremented by the value in response to completing the operation to modify the file.
    Type: Grant
    Filed: November 14, 2014
    Date of Patent: April 18, 2017
    Assignee: INTEL CORPORATION
    Inventors: William A. Stevens, Jr., Nitin V. Sarangdhar
  • Patent number: 9619573
    Abstract: Method for calculating tolerance zones for utility assets includes: receiving data about a point, a line, or an area related to a location of an utility asset in a region; receiving information about said utility asset in the region from one or more databases, wherein the received information includes two or more of a type of the utility asset, a location of the utility asset, an accuracy of the location of the utility asset, accuracy requirements for the utility asset, accuracy requirements for the region, and a map tile accuracy; calculating a tolerance zone for said utility asset in the region based on the accuracy requirements for the utility asset and one or more of said accuracy of the location of the utility asset, accuracy requirements for the region, and the map tile accuracy; and transmitting the tolerance zone to a remote device.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: April 11, 2017
    Assignee: PROSTAR GEOCORP, INC.
    Inventors: Nelson Page Tucker, Daniel Edward Colby, Peter James Lynch Forster, William Steven Slusarenko
  • Patent number: 9525555
    Abstract: In one embodiment, a processor has at least one core to execute instructions, a security engine coupled to the at least one core, a first storage to store a first immutable key associated with a vendor of the processor, and a second storage to store a second immutable key associated with an original equipment manufacturer (OEM) of the system. A first portion of firmware is to be verified based at least in part on the first immutable key and a second portion of firmware is to be verified based at least in part on the second immutable key, the first portion of firmware associated with the vendor and the second portion of firmware associated with the OEM. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 18, 2014
    Date of Patent: December 20, 2016
    Assignee: Intel Corporation
    Inventors: Prashant Dewan, Kapil Sood, Kumar N. Dwarakanath, Ioannis T. Schoinas, William A. Stevens, Jr., Ned M. Smith
  • Patent number: 9411748
    Abstract: Embodiments of the invention create an underlying infrastructure in a flash memory device (e.g., a serial peripheral interface (SPI) flash memory device) such that it may be protected against user attacks—e.g., replacing the SPI flash memory device or a man-in-the-middle (MITM) attack to modify the SPI flash memory contents on the fly. In the prior art, monotonic counters cannot be stored in SPI flash memory devices because said devices do not provide replay protection for the counters. A user may also remove the flash memory device and reprogram it. Host platforms alone cannot protect against such hardware attacks. Embodiments of the invention enable secure standard storage flash memory devices such as SPI flash memory devices to achieve replay protection for securely stored data. Embodiments of the invention utilize flash memory controllers, flash memory devices, unique device keys and HMAC key logic to create secure execution environments for various components.
    Type: Grant
    Filed: September 28, 2012
    Date of Patent: August 9, 2016
    Assignee: Intel Corporation
    Inventors: Nitin V. Sarangdhar, William A. Stevens, Jr., John J. Vranich
  • Patent number: 9405707
    Abstract: Embodiments of the invention create an underlying infrastructure in a flash memory device (e.g., a serial peripheral interface (SPI) flash memory device) such that it may be protected against user attacks—e.g., replacing the SPI flash memory device or a man-in-the-middle (MITM) attack to modify the SPI flash memory contents on the fly. In the prior art, monotonic counters cannot be stored in SPI flash memory devices because said devices do not provide replay protection for the counters. A user may also remove the flash memory device and reprogram it. Host platforms alone cannot protect against such hardware attacks. Embodiments of the invention enable secure standard storage flash memory devices such as SPI flash memory devices to achieve replay protection for securely stored data. Embodiments of the invention utilize flash memory controllers, flash memory devices, unique device keys and HMAC key logic to create secure execution environments for various components.
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: August 2, 2016
    Assignee: Intel Corporation
    Inventors: Nitin V. Sarangdhar, William A. Stevens, Jr., John J. Vranich
  • Publication number: 20160182238
    Abstract: In one embodiment, a processor has at least one core to execute instructions, a security engine coupled to the at least one core, a first storage to store a first immutable key associated with a vendor of the processor, and a second storage to store a second immutable key associated with an original equipment manufacturer (OEM) of the system. A first portion of firmware is to be verified based at least in part on the first immutable key and a second portion of firmware is to be verified based at least in part on the second immutable key, the first portion of firmware associated with the vendor and the second portion of firmware associated with the OEM. Other embodiments are described and claimed.
    Type: Application
    Filed: December 18, 2014
    Publication date: June 23, 2016
    Inventors: Prashant Dewan, Kapil Sood, Kumar N. Dwarakanath, Ioannis T. Schoinas, William A. Stevens, JR., Ned M. Smith
  • Publication number: 20160139808
    Abstract: Provided are a system, memory controller, and method for using counters and a table to protect data in a storage device. Upon initiating operations to modify a file in the storage device, a storage write counter is incremented in response to initiating the operations to modify the file. In response to incrementing the storage write counter, write table operations are initiated including setting a table write counter to a storage write counter and setting a table commit counter to the storage commit counter plus a value. The operation to modify the file in response to completing the write table operations. The system commit counter is incremented by the value in response to completing the operation to modify the file.
    Type: Application
    Filed: November 14, 2014
    Publication date: May 19, 2016
    Inventors: William A. STEVENS, JR., Nitin V. SARANGDHAR
  • Patent number: 9319224
    Abstract: The present disclosure is generally related to embedding public key infrastructure information to a system-on-chip (SOC). The method includes generating a key pair including a public key and a private key. The method includes creating a digital certificate corresponding to the public key. The method includes signing the digital certificate with a unique signature. The method includes extracting the public key and the unique signature into a key file, wherein the key file is to be stored in a plurality of silicon fuses on the SOC.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: April 19, 2016
    Assignee: Intel Corporation
    Inventors: Daniel Nemiroff, William Stevens, Jr.
  • Publication number: 20160059458
    Abstract: An injection molding machine comprises a manifold plate, a nozzle extending through the manifold plate, and a gate pad. A valve stem is disposed within the nozzle and is movable between a first position in which the valve stem extends through an outlet of the nozzle, and a retracted position. The gate pad has an inlet end with an inlet opening and an outlet end with a gate aperture. The inlet end is removably attachable to the manifold plate so that the nozzle is received through the inlet opening and the outlet of the nozzle is in communication with the gate aperture, wherein the valve stem seals the gate aperture in the extended position. The outlet end of the gate pad abuts a mold insert and molding material is delivered from the nozzle to a cavity defined by the mold insert through the gate aperture.
    Type: Application
    Filed: August 29, 2014
    Publication date: March 3, 2016
    Inventors: William Steven KEIR, Hakimuddin BOXWALA
  • Patent number: 9272453
    Abstract: An injection molding machine comprises a manifold plate, a nozzle extending through the manifold plate, and a gate pad. A valve stem is disposed within the nozzle and is movable between a first position in which the valve stem extends through an outlet of the nozzle, and a retracted position. The gate pad has an inlet end with an inlet opening and an outlet end with a gate aperture. The inlet end is removably attachable to the manifold plate so that the nozzle is received through the inlet opening and the outlet of the nozzle is in communication with the gate aperture, wherein the valve stem seals the gate aperture in the extended position. The outlet end of the gate pad abuts a mold insert and molding material is delivered from the nozzle to a cavity defined by the mold insert through the gate aperture.
    Type: Grant
    Filed: August 29, 2014
    Date of Patent: March 1, 2016
    Assignee: Husky Injection Molding Systems Ltd.
    Inventors: William Steven Keir, Hakimuddin Boxwala