Patents by Inventor Willm Hinrichs
Willm Hinrichs has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11775444Abstract: Driving address translations in a microprocessor system by sending a rejected Lx+1 cache request from a first set of caches of a first level Lx to a central request unit, transferring an Lx+1 cache request having a translation of a virtual address into a physical address stored in a first buffer, from the central request unit to the at least one Lx+1 cache, and keeping an Lx+1 cache request lacking a translation of a virtual address into a physical address stored in the first buffer, pending in the central request unit.Type: GrantFiled: March 15, 2022Date of Patent: October 3, 2023Assignee: International Business Machines CorporationInventors: Willm Hinrichs, Markus Kaltenbach, Simon Hermann Friedmann, Joerg Deutschle, Thomas G. Koehler
-
Publication number: 20230297515Abstract: Driving address translations in a microprocessor system by sending a rejected Lx+1 cache request from a first set of caches of a first level Lx to a central request unit, transferring an Lx+1 cache request having a translation of a virtual address into a physical address stored in a first buffer, from the central request unit to the at least one Lx+1 cache, and keeping an Lx+1 cache request lacking a translation of a virtual address into a physical address stored in the first buffer, pending in the central request unit.Type: ApplicationFiled: March 15, 2022Publication date: September 21, 2023Inventors: Willm Hinrichs, Markus Kaltenbach, Simon Hermann Friedmann, Joerg Deutschle, Thomas G. Koehler
-
Patent number: 10970214Abstract: A first request is received to access a first set of data in a first cache. A likelihood that a second request to a second cache for the first set of data will be canceled is determined. Access to the first set of data is completed based on the determining the likelihood that the second request to the second cache for the first set of data will be canceled.Type: GrantFiled: June 10, 2019Date of Patent: April 6, 2021Assignee: International Business Machines CorporationInventors: Willm Hinrichs, Markus Kaltenbach, Eyal Naor, Martin Recktenwald
-
Patent number: 10956328Abstract: A first request is received to access a first set of data in a first cache. A likelihood that a second request to a second cache for the first set of data will be canceled is determined. Access to the first set of data is completed based on the determining the likelihood that the second request to the second cache for the first set of data will be canceled.Type: GrantFiled: June 10, 2019Date of Patent: March 23, 2021Assignee: International Business Machines CorporationInventors: Willm Hinrichs, Markus Kaltenbach, Eyal Naor, Martin Recktenwald
-
Patent number: 10949351Abstract: In an approach to tracking and invalidating memory address synonyms in a memory system includes establishing a bits register for a first virtual address in a memory system, the bits register having synonym fields representing each bit of a first synonym identifier portion of the first virtual address, the first virtual address being mapped to a physical address; determining, for a second virtual address mapped to the physical address, the second virtual address having a second synonym identifier portion, a set of differing bits within the second synonym identifier portion compared to the first synonym identifier portion; and registering the set of differing bits in the bits register.Type: GrantFiled: April 25, 2019Date of Patent: March 16, 2021Assignee: International Business Machines CorporationInventors: Martin Recktenwald, Willm Hinrichs
-
Publication number: 20190294543Abstract: A first request is received to access a first set of data in a first cache. A likelihood that a second request to a second cache for the first set of data will be canceled is determined. Access to the first set of data is completed based on the determining the likelihood that the second request to the second cache for the first set of data will be canceled.Type: ApplicationFiled: June 10, 2019Publication date: September 26, 2019Inventors: Willm Hinrichs, Markus Kaltenbach, Eyal Naor, Martin Recktenwald
-
Publication number: 20190294544Abstract: A first request is received to access a first set of data in a first cache. A likelihood that a second request to a second cache for the first set of data will be canceled is determined. Access to the first set of data is completed based on the determining the likelihood that the second request to the second cache for the first set of data will be canceled.Type: ApplicationFiled: June 10, 2019Publication date: September 26, 2019Inventors: Willm Hinrichs, Markus Kaltenbach, Eyal Naor, Martin Recktenwald
-
Patent number: 10417127Abstract: A first request is received to access a first set of data in a first cache. A likelihood that a second request to a second cache for the first set of data will be canceled is determined. Access to the first set of data is completed based on the determining the likelihood that the second request to the second cache for the first set of data will be canceled.Type: GrantFiled: July 13, 2017Date of Patent: September 17, 2019Assignee: International Business Machines CorporationInventors: Willm Hinrichs, Markus Kaltenbach, Eyal Naor, Martin Recktenwald
-
Patent number: 10409724Abstract: A first request is received to access a first set of data in a first cache. A likelihood that a second request to a second cache for the first set of data will be canceled is determined. Access to the first set of data is completed based on the determining the likelihood that the second request to the second cache for the first set of data will be canceled.Type: GrantFiled: November 15, 2017Date of Patent: September 10, 2019Assignee: International Business Machines CorporationInventors: Willm Hinrichs, Markus Kaltenbach, Eyal Naor, Martin Recktenwald
-
Publication number: 20190251030Abstract: In an approach to tracking and invalidating memory address synonyms in a memory system includes establishing a bits register for a first virtual address in a memory system, the bits register having synonym fields representing each bit of a first synonym identifier portion of the first virtual address, the first virtual address being mapped to a physical address; determining, for a second virtual address mapped to the physical address, the second virtual address having a second synonym identifier portion, a set of differing bits within the second synonym identifier portion compared to the first synonym identifier portion; and registering the set of differing bits in the bits register.Type: ApplicationFiled: April 25, 2019Publication date: August 15, 2019Inventors: Martin Recktenwald, Willm Hinrichs
-
Publication number: 20190213129Abstract: A first request is received to access a first set of data in a first cache. A likelihood that a second request to a second cache for the first set of data will be canceled is determined. Access to the first set of data is completed based on the determining the likelihood that the second request to the second cache for the first set of data will be canceled.Type: ApplicationFiled: March 19, 2019Publication date: July 11, 2019Inventors: Willm Hinrichs, Markus Kaltenbach, Eyal Naor, Martin Recktenwald
-
Patent number: 10324847Abstract: A method for tracking and invalidating memory address synonyms in a cache memory system includes receiving a request to associate a second memory address with a first memory address in a cache memory system that supports synonyms, wherein the second memory address and the first memory address each comprise a synonym identifier. The method also includes determining a set of differing bits within the synonym identifier of the first memory address and the second memory address, and including the set of differing bits within a set of synonym generation bits for the cache memory system. A corresponding apparatus, computer program product, and system are also disclosed herein.Type: GrantFiled: November 29, 2017Date of Patent: June 18, 2019Assignee: International Business Machines CorporationInventors: Martin Recktenwald, Willm Hinrichs
-
Patent number: 10324846Abstract: A method for tracking and invalidating memory address synonyms in a cache memory system includes receiving a request to associate a second memory address with a first memory address in a cache memory system that supports synonyms, wherein the second memory address and the first memory address each comprise a synonym identifier. The method also includes determining a set of differing bits within the synonym identifier of the first memory address and the second memory address, and including the set of differing bits within a set of synonym generation bits for the cache memory system. A corresponding apparatus, computer program product, and system are also disclosed herein.Type: GrantFiled: September 21, 2017Date of Patent: June 18, 2019Assignee: International Business Machines CorporationInventors: Martin Recktenwald, Willm Hinrichs
-
Publication number: 20190087338Abstract: A method for tracking and invalidating memory address synonyms in a cache memory system includes receiving a request to associate a second memory address with a first memory address in a cache memory system that supports synonyms, wherein the second memory address and the first memory address each comprise a synonym identifier. The method also includes determining a set of differing bits within the synonym identifier of the first memory address and the second memory address, and including the set of differing bits within a set of synonym generation bits for the cache memory system. A corresponding apparatus, computer program product, and system are also disclosed herein.Type: ApplicationFiled: September 21, 2017Publication date: March 21, 2019Inventors: Martin Recktenwald, Willm Hinrichs
-
Publication number: 20190087339Abstract: A method for tracking and invalidating memory address synonyms in a cache memory system includes receiving a request to associate a second memory address with a first memory address in a cache memory system that supports synonyms, wherein the second memory address and the first memory address each comprise a synonym identifier. The method also includes determining a set of differing bits within the synonym identifier of the first memory address and the second memory address, and including the set of differing bits within a set of synonym generation bits for the cache memory system. A corresponding apparatus, computer program product, and system are also disclosed herein.Type: ApplicationFiled: November 29, 2017Publication date: March 21, 2019Inventors: Martin Recktenwald, Willm Hinrichs
-
Publication number: 20190018773Abstract: A first request is received to access a first set of data in a first cache. A likelihood that a second request to a second cache for the first set of data will be canceled is determined. Access to the first set of data is completed based on the determining the likelihood that the second request to the second cache for the first set of data will be canceled.Type: ApplicationFiled: November 15, 2017Publication date: January 17, 2019Inventors: Willm Hinrichs, Markus Kaltenbach, Eyal Naor, Martin Recktenwald
-
Publication number: 20190018772Abstract: A first request is received to access a first set of data in a first cache. A likelihood that a second request to a second cache for the first set of data will be canceled is determined. Access to the first set of data is completed based on the determining the likelihood that the second request to the second cache for the first set of data will be canceled.Type: ApplicationFiled: July 13, 2017Publication date: January 17, 2019Inventors: Willm Hinrichs, Markus Kaltenbach, Eyal Naor, Martin Recktenwald
-
Patent number: 9886395Abstract: A tool for determining eviction of store cache entries based on store pressure. The tool determines, by one or more computer processors, a count value for one or more new store cache entry allocations. The tool determines whether a new store cache entry allocation limit is exceeded. Responsive to determining the new store cache entry allocation limit is exceeded, the tool determines an allocation value for one or more existing store cache entries, the allocation value indicating an allocation class for each of the one or more existing store cache entries. The tool determines based, at least in part, on the allocation value for the one or more existing store cache entries, at least one allocation class for eviction. The tool program determines an eviction request setting for evicting the one or more existing store cache entries.Type: GrantFiled: November 12, 2015Date of Patent: February 6, 2018Assignee: International Business Machines CorporationInventors: Uwe Brandt, Willm Hinrichs, Walter Lipponer, Martin Recktenwald, Hans-Werner Tast
-
Patent number: 9658967Abstract: A tool for determining eviction of store cache entries based on store pressure. The tool determines, by one or more computer processors, a count value for one or more new store cache entry allocations. The tool determines, by one or more computer processors, whether a new store cache entry allocation limit is exceeded. Responsive to determining the new store cache entry allocation limit is exceeded, the tool determines, by one or more computer processors, an allocation value for one or more existing store cache entries, the allocation value indicating an allocation class for each of the one or more existing store cache entries. The tool determines, by one or more computer processors based, at least in part, on the allocation value for the one or more existing store cache entries, at least one allocation class for eviction. The tool program determines, by one or more computer processors, an eviction request setting for evicting the one or more existing store cache entries.Type: GrantFiled: June 25, 2014Date of Patent: May 23, 2017Assignee: International Business Machines CorporationInventors: Uwe Brandt, Willm Hinrichs, Walter Lipponer, Martin Recktenwald, Hans-Werner Tast
-
Patent number: 9626293Abstract: Cache miss rates for threads operating in a simultaneous multi-threading computer processing environment can be estimated. The single thread rates can be estimated by monitoring a shared directory for cache misses for a first thread. Memory access requests can be routed to metering cache directories associated with the particular thread. Single thread misses to the shared directory and single thread misses to the associated metering cache directory are monitored and a performance indication is determined by comparing the cache misses with the thread misses. The directory in the associated metering cache is rotated, and a second sharing performance indication is determined.Type: GrantFiled: October 21, 2015Date of Patent: April 18, 2017Assignee: International Business Machines CorporationInventors: James J. Bonanno, Alper Buyuktosunoglu, Brian W. Curran, Willm Hinrichs, Christian Jacobi, Brian R. Prasky, Martin Recktenwald, Anthony Saporito, Vijayalakshmi Srinivasan, John-David Wellman