Patents by Inventor Willm Hinrichs
Willm Hinrichs has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9619385Abstract: Cache miss rates for threads operating in a simultaneous multi-threading computer processing environment can be estimated. The single thread rates can be estimated by monitoring a shared directory for cache misses for a first thread. Memory access requests can be routed to metering cache directories associated with the particular thread. Single thread misses to the shared directory and single thread misses to the associated metering cache directory are monitored and a performance indication is determined by comparing the cache misses with the thread misses. The directory in the associated metering cache is rotated, and a second sharing performance indication is determined.Type: GrantFiled: February 25, 2015Date of Patent: April 11, 2017Assignee: International Business Machines CorporationInventors: James J. Bonanno, Alper Buyuktosunoglu, Brian W. Curran, Willm Hinrichs, Christian Jacobi, Brian R. Prasky, Martin Recktenwald, Anthony Saporito, Vijayalakshmi Srinivasan, John-David Wellman
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Patent number: 9588893Abstract: A method to merge one or more non-transactional stores and one or more thread-specific transactional stores into one or more cache line templates in a store buffer in a store cache. The method receives a thread-specific non-transactional store address and a first data, maps the store address to a first cache line template, and merges the first data into the first cache line template, according to a store policy. The method further receives a thread-specific transactional store address and a second data, maps the thread-specific store address into a second cache line template, according to a store policy. The method further writes back a copy of a cache line template to a cache and invalidates a third cache line template, which frees the third cache line template from a store address mapping.Type: GrantFiled: November 10, 2014Date of Patent: March 7, 2017Assignee: International Business Machines CorporationInventors: Uwe Brandt, Willm Hinrichs, Walter Lipponer, Martin Recktenwald, Hans-Werner Tast
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Patent number: 9588894Abstract: A method to merge one or more non-transactional stores and one or more thread-specific transactional stores into one or more cache line templates in a store buffer in a store cache. The method receives a thread-specific non-transactional store address and a first data, maps the store address to a first cache line template, and merges the first data into the first cache line template, according to a store policy. The method further receives a thread-specific transactional store address and a second data, maps the thread-specific store address into a second cache line template, according to a store policy. The method further writes back a copy of a cache line template to a cache and invalidates a third cache line template, which frees the third cache line template from a store address mapping.Type: GrantFiled: December 22, 2014Date of Patent: March 7, 2017Assignee: International Business Machines CorporationInventors: Uwe Brandt, Willm Hinrichs, Walter Lipponer, Martin Recktenwald, Hans-Werner Tast
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Publication number: 20160246716Abstract: Cache miss rates for threads operating in a simultaneous multi-threading computer processing environment can be estimated. The single thread rates can be estimated by monitoring a shared directory for cache misses for a first thread. Memory access requests can be routed to metering cache directories associated with the particular thread. Single thread misses to the shared directory and single thread misses to the associated metering cache directory are monitored and a performance indication is determined by comparing the cache misses with the thread misses. The directory in the associated metering cache is rotated, and a second sharing performance indication is determined.Type: ApplicationFiled: October 21, 2015Publication date: August 25, 2016Inventors: James J. Bonanno, Alper Buyuktosunoglu, Brian W. Curran, Willm Hinrichs, Christian Jacobi, Brian R. Prasky, Martin Recktenwald, Anthony Saporito, Vijayalakshmi Srinivasan, John-David Wellman
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Publication number: 20160246722Abstract: Cache miss rates for threads operating in a simultaneous multi-threading computer processing environment can be estimated. The single thread rates can be estimated by monitoring a shared directory for cache misses for a first thread. Memory access requests can be routed to metering cache directories associated with the particular thread. Single thread misses to the shared directory and single thread misses to the associated metering cache directory are monitored and a performance indication is determined by comparing the cache misses with the thread misses. The directory in the associated metering cache is rotated, and a second sharing performance indication is determined.Type: ApplicationFiled: February 25, 2015Publication date: August 25, 2016Inventors: James J. Bonanno, Alper Buyuktosunoglu, Brian W. Curran, Willm Hinrichs, Christian Jacobi, Brian R. Prasky, Martin Recktenwald, Anthony Saporito, Vijayalakshmi Srinivasan, John-David Wellman
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Publication number: 20160132434Abstract: A method to merge one or more non-transactional stores and one or more thread-specific transactional stores into one or more cache line templates in a store buffer in a store cache. The method receives a thread-specific non-transactional store address and a first data, maps the store address to a first cache line template, and merges the first data into the first cache line template, according to a store policy. The method further receives a thread-specific transactional store address and a second data, maps the thread-specific store address into a second cache line template, according to a store policy. The method further writes back a copy of a cache line template to a cache and invalidates a third cache line template, which frees the third cache line template from a store address mapping.Type: ApplicationFiled: November 10, 2014Publication date: May 12, 2016Inventors: Uwe Brandt, Willm Hinrichs, Walter Lipponer, Martin Recktenwald, Hans-Werner Tast
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Publication number: 20160132431Abstract: A method to merge one or more non-transactional stores and one or more thread-specific transactional stores into one or more cache line templates in a store buffer in a store cache. The method receives a thread-specific non-transactional store address and a first data, maps the store address to a first cache line template, and merges the first data into the first cache line template, according to a store policy. The method further receives a thread-specific transactional store address and a second data, maps the thread-specific store address into a second cache line template, according to a store policy. The method further writes back a copy of a cache line template to a cache and invalidates a third cache line template, which frees the third cache line template from a store address mapping.Type: ApplicationFiled: December 22, 2014Publication date: May 12, 2016Inventors: Uwe Brandt, Willm Hinrichs, Walter Lipponer, Martin Recktenwald, Hans-Werner Tast
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Publication number: 20160070654Abstract: A tool for determining eviction of store cache entries based on store pressure. The tool determines, by one or more computer processors, a count value for one or more new store cache entry allocations. The tool determines whether a new store cache entry allocation limit is exceeded. Responsive to determining the new store cache entry allocation limit is exceeded, the tool determines an allocation value for one or more existing store cache entries, the allocation value indicating an allocation class for each of the one or more existing store cache entries. The tool determines based, at least in part, on the allocation value for the one or more existing store cache entries, at least one allocation class for eviction. The tool program determines an eviction request setting for evicting the one or more existing store cache entries.Type: ApplicationFiled: November 12, 2015Publication date: March 10, 2016Inventors: Uwe Brandt, Willm Hinrichs, Walter Lipponer, Martin Recktenwald, Hans-Werner Tast
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Publication number: 20150378924Abstract: A tool for determining eviction of store cache entries based on store pressure. The tool determines, by one or more computer processors, a count value for one or more new store cache entry allocations. The tool determines, by one or more computer processors, whether a new store cache entry allocation limit is exceeded. Responsive to determining the new store cache entry allocation limit is exceeded, the tool determines, by one or more computer processors, an allocation value for one or more existing store cache entries, the allocation value indicating an allocation class for each of the one or more existing store cache entries. The tool determines, by one or more computer processors based, at least in part, on the allocation value for the one or more existing store cache entries, at least one allocation class for eviction. The tool program determines, by one or more computer processors, an eviction request setting for evicting the one or more existing store cache entries.Type: ApplicationFiled: June 25, 2014Publication date: December 31, 2015Inventors: Uwe Brandt, Willm Hinrichs, Walter Lipponer, Martin Recktenwald, Hans-Werner Tast
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Patent number: 9104364Abstract: An indication of time that indicates at least one of the current day and the current time is received. It is determined that a raw interval pulse transmitted by a first oscillator should be adjusted based, at least partly, on the indication of time. In response to determining that the raw interval pulse should be adjusted, a steered time interval pulse is generated based, at least partly, on the raw time interval pulse and the indication of time. The steered time interval pulse is distributed to a plurality of hardware components.Type: GrantFiled: November 15, 2012Date of Patent: August 11, 2015Assignee: International Business Machines CorporationInventors: Eberhard Engler, Guenter Gerwig, Willm Hinrichs, Barinjato Ramanandray
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Publication number: 20140136877Abstract: An apparatus comprising a first oscillator, a time source controller coupled with the first oscillator and corrected time interval counters coupled with the time source controller. The first oscillator is configured to transmit a raw time interval pulse at regular or near regular intervals. The time source controller is configured to receive an indication of time that indicates at least one of the current day and the current time and to determine that the raw interval pulse should be adjusted based on the indication of time. The time source controller is also configured to generate a steered time interval pulse based, at least partly, on the raw time interval pulse and the indication of time, and distribute the steered time interval pulse to a plurality of hardware components. The time interval counters are configured to host a time value based on the output from the time source controller.Type: ApplicationFiled: November 15, 2012Publication date: May 15, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Eberhard Engler, Guenter Gerwig, Willm Hinrichs, Barinjato Ramanandray
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Patent number: 8363487Abstract: An improved method monitors memory circuits, especially those used in integrated circuits. The method provides: writing random data in at least one monitor cell, which is implemented as a regular memory cell with an artificially deteriorated stability in order to provoke early fails when compared to fails in a regular memory cell; reading the random data out of the at least one monitor cell; comparing the output data of the read operation against an expected value to detect a value mismatch; and reporting the value mismatch to an error structure if the value mismatch is detected.Type: GrantFiled: May 20, 2010Date of Patent: January 29, 2013Assignee: International Business Machines CorporationInventors: Sebastian Ehrenreich, Tilman Gloekler, Willm Hinrichs, Jens Kuenzer
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Patent number: 8055931Abstract: A method is provided for switching between two oscillator signals within an alignment element. In accordance with the method, one of the two oscillator signals one is selected as a first master signal in order to provide an output stepping signal at an output of the alignment element. The method comprises introducing a virtual stepping signal when a switch between the two oscillator signals occurs or when a failure in the first master signal is detected. The method further comprises sending the virtual stepping signal to the output of the alignment element in the event of a switch until an alignment with a new master signal is completed.Type: GrantFiled: October 6, 2008Date of Patent: November 8, 2011Assignee: International Business Machines CorporationInventors: Ralf Ludewig, Thuyen Le, Tilman Gloekler, Willm Hinrichs
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Patent number: 7983372Abstract: The present invention relates to a method, computer program product and system for generating a sample signal from differing clock domain boundaries. The system comprises a cycle base component, a sample offset component being configured to receive a time-based sample pulse signal, and logic to generate a sample pulse. The sample pulse generation logic is configured to receive a time-based sample pulse signal, a free running counter value, a sample offset counter value, and deliver a sample pulse signal.Type: GrantFiled: February 14, 2008Date of Patent: July 19, 2011Assignee: International Business Machines CorporationInventors: Jane H. Bartik, Willm Hinrichs, Martin Recktenwald, Patrick M. West, Jr.
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Patent number: 7881906Abstract: A system, method and computer program product for event-based sampling to monitor computer system performance are provided. The system includes a sample buffer to store a sample of instrumentation data, where the instrumentation data enables measurement of computer system performance. The system also includes a sample segment selector to isolate a segment of the sample of instrumentation data as an event. The system further includes an instrumentation counter counting in response to a combination of the event and a sample pulse, and asserting a sample interrupt indicating that the sample of instrumentation data is ready to logout from the sample buffer.Type: GrantFiled: February 15, 2008Date of Patent: February 1, 2011Assignee: International Business Machines CorporationInventors: Jane H. Bartik, Willm Hinrichs, Martin Recktenwald, Patrick M. West, Jr.
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Publication number: 20100309734Abstract: An improved method monitors memory circuits, especially those used in integrated circuits. The method provides: writing random data in at least one monitor cell, which is implemented as a regular memory cell with an artificially deteriorated stability in order to provoke early fails when compared to fails in a regular memory cell; reading the random data out of the at least one monitor cell; comparing the output data of the read operation against an expected value to detect a value mismatch; and reporting the value mismatch to an error structure if the value mismatch is detected.Type: ApplicationFiled: May 20, 2010Publication date: December 9, 2010Applicant: IBM CorporationInventors: Sebastian Ehrenreich, Tilman Gloekler, Willm Hinrichs, Jens Kuenzer
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Publication number: 20090207958Abstract: The present invention relates to a method, computer program product and system for generating a sample signal from differing clock domain boundaries. The system comprises a cycle base component, a sample offset component being configured to receive a time-based sample pulse signal, and logic to generate a sample pulse. The sample pulse generation logic is configured to receive a time-based sample pulse signal, a free running counter value, a sample offset counter value, and deliver a sample pulse signal.Type: ApplicationFiled: February 14, 2008Publication date: August 20, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jane H. Bartik, Willm Hinrichs, Martin Recktenwald, Patrick M. West, JR.
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Publication number: 20090210196Abstract: A system, method and computer program product for event-based sampling to monitor computer system performance are provided. The system includes a sample buffer to store a sample of instrumentation data, where the instrumentation data enables measurement of computer system performance. The system also includes a sample segment selector to isolate a segment of the sample of instrumentation data as an event. The system further includes an instrumentation counter counting in response to a combination of the event and a sample pulse, and asserting a sample interrupt indicating that the sample of instrumentation data is ready to logout from the sample buffer.Type: ApplicationFiled: February 15, 2008Publication date: August 20, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jane H. Bartik, Willm Hinrichs, Martin Recktenwald, Patrick M. West, JR.
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Publication number: 20090100283Abstract: A method for switching between two oscillator signals within an alignment element, wherein one of the two oscillator signals one is selected as a first master signal in order to provide an output stepping signal at an output of the alignment element. Said method comprises the steps of: introducing a virtual stepping signal when a switch between the two oscillator signals occurs or when a failure in the first master signal is detected; sending the virtual stepping signal to the output of the alignment element in the event of a switch until an alignment with a new master signal is completed; sending the virtual stepping signal to the output of the alignment element in the event of a failure in the master signal until a switch to the other oscillator signal as a new master signal is performed or until the first master signal becomes valid again.Type: ApplicationFiled: October 6, 2008Publication date: April 16, 2009Applicant: International Business Machines CorporationInventors: Ralf Ludewig, Thuyen Le, Tilman Gloekler, Willm Hinrichs
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Publication number: 20080115004Abstract: A clock skew adjustment arrangement for a chip is provided which chip is subdivided in at least two blocks, wherein the blocks are supplied with a clock signal of a single joint clock signal generator via clock signals paths, and wherein to each block a circuitry is assigned for measuring and adjusting the respective clock signal.Type: ApplicationFiled: November 13, 2007Publication date: May 15, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Florian Braun, Willm Hinrichs, Cedric Lichtenau, Thomas Pflueger