Abstract: An apparatus relates generally to a microelectronic package. In such an apparatus, a microelectronic die has a first surface, a second surface opposite the first surface, and a sidewall surface between the first and second surfaces. A plurality of wire bond wires with proximal ends thereof are coupled to either the first surface or the second surface of the microelectronic die with distal ends of the plurality of wire bond wires extending away from either the first surface or the second surface, respectively, of the microelectronic die. A portion of the plurality of wire bond wires extends outside a perimeter of the microelectronic die into a fan-out (“FO”) region. A molding material covers the first surface, the sidewall surface, and portions of the plurality of the wire bond wires from the first surface of the microelectronic die to an outer surface of the molding material.

Abstract: An apparatus relates generally to a microelectromechanical system component. In such an apparatus, the microelectromechanical system component has a lower surface, an upper surface, first side surfaces, and second side surfaces. Surface area of the first side surfaces is greater than surface area of the second side surfaces. The microelectromechanical system component has a plurality of wire bond wires attached to and extending away from a first side surface of the first side surfaces. The wire bond wires are self-supporting and cantilevered with respect to the first side surface of the first side surfaces.

Abstract: A semiconductor assembly comprising an integrated circuit chip with a first plurality of metallic contact pads exposed, having a pitch center-to-center of less than 180 ?m. A metallic bump of reflowable metal is attached to each of these contact pads. The assembly further has an electrically insulating substrate with a second plurality of metallic terminal pads in locations matching the locations of the contact pads. Each of the bumps also attached to these matching terminal pads, respectively, whereby the chip is interconnected with the substrate spaced apart by a gap. An adherent polymeric encapsulant fills the gap so that the encapsulant is free of voids. It is a pivotal feature in the method that vibration energy, up to ultrasonic frequencies, is used while the encapsulant is still in a low-viscosity precursor state in order to ensure the void-free spreading of the precursor throughout the gap between chip and substrate.

Abstract: A semiconductor assembly comprising an integrated circuit chip with a first plurality of metallic contact pads exposed, having a pitch center-to-center of less than 180 ?m. A metallic bump of reflowable metal is attached to each of these contact pads. The assembly further has an electrically insulating substrate with a second plurality of metallic terminal pads in locations matching the locations of the contact pads. Each of the bumps also attached to these matching terminal pads, respectively, whereby the chip is interconnected with the substrate spaced apart by a gap. An adherent polymeric encapsulant fills the gap so that the encapsulant is free of voids. It is a pivotal feature in the method that vibration energy, up to ultrasonic frequencies, is used while the encapsulant is still in a low-viscosity precursor state in order to ensure the void-free spreading of the precursor throughout the gap between chip and substrate.

Abstract: A robust, reliable and low-cost metal structure and process enabling electrical wire/ribbon connections to the interconnecting copper metallization of integrated circuits. The structure comprises a layer of barrier metal that resists copper diffusion, deposited on the non-oxidized copper surface in a thickness such that the barrier layer reduces the diffusion of copper at 250° C. by more than 80% compared with the absence of the barrier metal. The structure further comprises an outermost bondable layer which reduces the diffusion of the barrier metal at 250° C. by more than 80% compared with the absence of the bondable metal. Finally, a metal wire is bonded to the outermost layer for metallurgical connection. The barrier metal is selected from a group consisting of nickel, cobalt, chromium, molybdenum, titanium, tungsten, and alloys thereof. The outermost bondable metal layer is selected from a group consisting of gold, platinum, and silver.

Abstract: The present invention provides a system and method for preparing semiconductor integrated circuits (“ICs”), particularly ball grid arrays (“BGAs”), quad flat packs (“QFPs”) and dual in line packages (“DIPs”) for failure analysis (“FA”) using a variety of techniques, including emission microscopy (“EM”) and externally induced voltage alteration (“XIVA”). This system and method requires precision thinning and polishing of the semiconductor IC device to expose the backside of the die and mounting of the semiconductor device on a secondary package assembly.

Abstract: A device having a thin metallic coating, such as tin which forms strong bonds to copper is provided on the bond pads of an integrated circuit having copper metallization; surface oxidation of the coating is self limiting and the oxides are readily removed, further the coated bond pad forms intermetallics at low temperatures making it both solderable and compatible with wire bonding. A low cost process for forming tin coated copper bonding pads is provided by electroless plating.

Abstract: A semiconductor assembly comprising a semiconductor chip having an active and a passive surface, said active surface including an integrated circuit and a plurality of bonding pads; said bonding pads having a metallization suitable for wire bonding; an array of interconnects of uniform height, each of said interconnects comprising a wire loop substantially perpendicular to said active surface, each of said loops having both wire ends attached to a bonding pad, respectively, and a major and a minor diameter, said loops being oriented parallel with regard to the plane of the opening and having constant offsets in both direction and magnitude of their apex relative to their bonding pad centers; said wire loops having sufficient elasticity to act as stress-absorbing springs; an electrically insulating substrate having first and second surfaces, a plurality of electrically conductive routing strips integral with said substrate, and a plurality of contact pads disposed on said first surface, with attachment materia