Patents by Inventor Wilman Tsai

Wilman Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12211836
    Abstract: A semiconductor device includes a first channel region disposed over a substrate, and a first gate structure disposed over the first channel region. The first gate structure includes a gate dielectric layer disposed over the channel region, a lower conductive gate layer disposed over the gate dielectric layer, a ferroelectric material layer disposed over the lower conductive gate layer, and an upper conductive gate layer disposed over the ferroelectric material layer. The ferroelectric material layer is in direct contact with the gate dielectric layer and the lower gate conductive layer, and has a U-shape cross section.
    Type: Grant
    Filed: June 27, 2023
    Date of Patent: January 28, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Wen Chang, Hong-Nien Lin, Chien-Hsing Lee, Chih-Sheng Chang, Ling-Yen Yeh, Wilman Tsai, Yee-Chia Yeo
  • Publication number: 20250024689
    Abstract: An magnetoresistive random access memory (MRAM) device includes a magnetic tunnel junction, and a spin-orbit torque material. Based on a current applied to the spin-orbit torque material, the spin-orbit torque material generates spin polarization along one or multiple axes.
    Type: Application
    Filed: July 9, 2024
    Publication date: January 16, 2025
    Applicants: SAMSUNG ELECTRONICS CO., LTD., The Board of Trustees of the Leland Stanford Junior University
    Inventors: William San-Hsi HWANG, Shan Xiang WANG, Fen Xue, Wilman TSAI, Harsono SIMKA
  • Patent number: 12166098
    Abstract: Ferroelectric materials and more particularly cerium-doped ferroelectric materials and related devices and methods are disclosed. Aspects of the present disclosure relate to ferroelectric layers of hafnium-zirconium-oxide (HZO) doped with cerium that enable reliable ferroelectric fabrication processes and related structures with significantly improved cycling endurance performance. Such doping in ferroelectric layers also provides the capability to modulate polarization to achieve a desired operation voltage range. Doping concentrations of cerium in HZO films are disclosed with ranges that provide a stabilized polar orthorhombic phase in resulting films, thereby promoting ferroelectric capabilities. Exemplary fabrication techniques for doping cerium in HZO films as well as exemplary device structures including metal-ferroelectric-metal (MFM) and metal-ferroelectric-insulator-semiconductor (MFIS) structures are also disclosed.
    Type: Grant
    Filed: November 23, 2021
    Date of Patent: December 10, 2024
    Assignee: The Board of Trustees of the Leland Stanford Junior University
    Inventors: Paul C. McIntyre, Wilman Tsai, John D. Baniecki, Zhouchangwan Yu, Balreen Saini
  • Publication number: 20240387090
    Abstract: Memory stacks, memory devices and method of forming the same are provided. A memory stack includes a spin-orbit torque layer, a magnetic bias layer and a free layer. The magnetic bias layer is in physical contact with the spin-orbit torque layer and has a first magnetic anisotropy. The free layer is disposed adjacent to the spin-orbit torque layer and has a second magnetic anisotropy perpendicular to the first magnetic anisotropy.
    Type: Application
    Filed: July 28, 2024
    Publication date: November 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shy-Jay Lin, Wilman Tsai, Ming-Yuan Song
  • Patent number: 12148829
    Abstract: In a method of manufacturing a negative capacitance structure, a ferroelectric dielectric layer is formed over a first conductive layer disposed over a substrate, and a second conductive layer is formed over the ferroelectric dielectric layer. The ferroelectric dielectric layer includes an amorphous layer and crystals.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: November 19, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wilman Tsai, Ling-Yen Yeh
  • Publication number: 20240379848
    Abstract: In a method of manufacturing a negative capacitance structure, a ferroelectric dielectric layer is formed over a first conductive layer disposed over a substrate, and a second conductive layer is formed over the ferroelectric dielectric layer. The ferroelectric dielectric layer includes an amorphous layer and crystals.
    Type: Application
    Filed: July 25, 2024
    Publication date: November 14, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wilman TSAI, Ling-Yen YEH
  • Publication number: 20240373647
    Abstract: A method includes depositing a plurality of layers, which includes depositing a spin orbit coupling layer, depositing a dielectric layer over the spin orbit coupling layer, depositing a free layer over the dielectric layer, depositing a tunnel barrier layer over the free layer, and depositing a reference layer over the tunnel barrier layer. The method further includes performing a first patterning process to pattern the plurality of layers, and performing a second patterning process to pattern the reference layer, the tunnel barrier layer, the free layer, and the dielectric layer. The second patterning process stops on a top surface of the spin orbit coupling layer.
    Type: Application
    Filed: July 16, 2024
    Publication date: November 7, 2024
    Inventors: Wilman Tsai, MingYuan Song, Shy-Jay Lin
  • Patent number: 12114510
    Abstract: A device includes a spin orbit coupling layer and a Magnetic Tunnel Junction (MTJ) stack. The MTJ stack includes a dielectric layer over the spin orbit coupling layer, a free layer over the dielectric layer, a tunnel barrier layer over the free laver, and a reference layer over the tunnel barrier layer. The spin orbit coupling layer extends beyond edges of the MTJ stack in a first direction and a second direction opposite to the first direction.
    Type: Grant
    Filed: June 30, 2022
    Date of Patent: October 8, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wilman Tsai, MingYuan Song, Shy-Jay Lin
  • Patent number: 11963366
    Abstract: A spin-orbit-torque (SOT) magnetic device includes a bottom metal layer, a first magnetic layer disposed over the bottom metal layer, a spacer layer disposed over the first magnetic layer, and a second magnetic layer disposed over the spacer layer. A diffusion barrier layer for suppressing metal elements of the first magnetic layer from diffusing into the bottom metal layer is disposed between the bottom metal layer and the first magnetic layer.
    Type: Grant
    Filed: July 27, 2022
    Date of Patent: April 16, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wilman Tsai, Shy-Jay Lin, Mingyuan Song
  • Publication number: 20240087786
    Abstract: Memory stacks, memory devices and method of forming the same are provided. A memory stack includes a spin-orbit torque layer, a magnetic bias layer and a free layer. The magnetic bias layer is in physical contact with the spin-orbit torque layer and has a first magnetic anisotropy. The free layer is disposed adjacent to the spin-orbit torque layer and has a second magnetic anisotropy perpendicular to the first magnetic anisotropy.
    Type: Application
    Filed: November 27, 2023
    Publication date: March 14, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shy-Jay Lin, Wilman Tsai, Ming-Yuan Song
  • Patent number: 11862732
    Abstract: Structures and formation methods of a semiconductor device structure are provided. The method includes providing a substrate having a first fin, and the first fin has a channel region and a source/drain region. The method includes forming a stack structure over the first fin, and the stack structure includes a first semiconductor layer and a second semiconductor layer vertically stacked over the fin. The method also includes removing a portion of the second semiconductor layer in the channel region, and a portion of the first semiconductor layer is remaining in the channel region. The method further includes forming a cladding layer over the remaining first semiconductor material layer in the channel region to form a nanostructure, wherein the nanostructure has a dumbbell shape. The method includes forming a gate structure surrounding the nanostructure.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: January 2, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wilman Tsai, Cheng-Hsien Wu, I-Sheng Chen, Stefan Rusu
  • Patent number: 11862373
    Abstract: Memory stacks, memory devices and method of forming the same are provided. A memory stack includes a spin-orbit torque layer, a magnetic bias layer and a free layer. The magnetic bias layer is in physical contact with the spin-orbit torque layer and has a first magnetic anisotropy. The free layer is disposed adjacent to the spin-orbit torque layer and has a second magnetic anisotropy perpendicular to the first magnetic anisotropy.
    Type: Grant
    Filed: July 29, 2022
    Date of Patent: January 2, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shy-Jay Lin, Wilman Tsai, Ming-Yuan Song
  • Publication number: 20230343781
    Abstract: A semiconductor device includes a first channel region disposed over a substrate, and a first gate structure disposed over the first channel region. The first gate structure includes a gate dielectric layer disposed over the channel region, a lower conductive gate layer disposed over the gate dielectric layer, a ferroelectric material layer disposed over the lower conductive gate layer, and an upper conductive gate layer disposed over the ferroelectric material layer. The ferroelectric material layer is in direct contact with the gate dielectric layer and the lower gate conductive layer, and has a U-shape cross section.
    Type: Application
    Filed: June 27, 2023
    Publication date: October 26, 2023
    Inventors: Chia-Wen CHANG, Hong-Nien LIN, Chien-Hsing LEE, Chih-Sheng CHANG, Ling_Yen YEH, Wilman TSAI, Yee-Chia YEO
  • Patent number: 11728332
    Abstract: A semiconductor device includes a first channel region disposed over a substrate, and a first gate structure disposed over the first channel region. The first gate structure includes a gate dielectric layer disposed over the channel region, a lower conductive gate layer disposed over the gate dielectric layer, a ferroelectric material layer disposed over the lower conductive gate layer, and an upper conductive gate layer disposed over the ferroelectric material layer. The ferroelectric material layer is in direct contact with the gate dielectric layer and the lower gate conductive layer, and has a U-shape cross section.
    Type: Grant
    Filed: June 21, 2021
    Date of Patent: August 15, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Wen Chang, Hong-Nien Lin, Chien-Hsing Lee, Chih-Sheng Chang, Ling-Yen Yeh, Wilman Tsai, Yee-Chia Yeo
  • Publication number: 20220375993
    Abstract: A spin-orbit-torque (SOT) magnetic device includes a bottom metal layer, a first magnetic layer disposed over the bottom metal layer, a spacer layer disposed over the first magnetic layer, and a second magnetic layer disposed over the spacer layer. A diffusion barrier layer for suppressing metal elements of the first magnetic layer from diffusing into the bottom metal layer is disposed between the bottom metal layer and the first magnetic layer.
    Type: Application
    Filed: July 27, 2022
    Publication date: November 24, 2022
    Inventors: Wilman TSAI, Shy-Jay LIN, Mingyuan SONG
  • Publication number: 20220367098
    Abstract: Memory stacks, memory devices and method of forming the same are provided. A memory stack includes a spin-orbit torque layer, a magnetic bias layer and a free layer. The magnetic bias layer is in physical contact with the spin-orbit torque layer and has a first magnetic anisotropy. The free layer is disposed adjacent to the spin-orbit torque layer and has a second magnetic anisotropy perpendicular to the first magnetic anisotropy.
    Type: Application
    Filed: July 29, 2022
    Publication date: November 17, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shy-Jay Lin, Wilman Tsai, Ming-Yuan Song
  • Publication number: 20220328559
    Abstract: A method includes depositing a plurality of layers, which includes depositing a spin orbit coupling layer, depositing a dielectric layer over the spin orbit coupling layer, depositing a free layer over the dielectric layer, depositing a tunnel barrier layer over the free layer, and depositing a reference layer over the tunnel barrier layer. The method further includes performing a first patterning process to pattern the plurality of layers, and performing a second patterning process to pattern the reference layer, the tunnel barrier layer, the free layer, and the dielectric layer. The second patterning process stops on a top surface of the spin orbit coupling layer.
    Type: Application
    Filed: June 30, 2022
    Publication date: October 13, 2022
    Inventors: Wilman Tsai, MingYuan Song, Shy-Jay Lin
  • Patent number: 11469267
    Abstract: A method includes depositing a plurality of layers, which includes depositing a spin orbit coupling layer, depositing a dielectric layer over the spin orbit coupling layer, depositing a free layer over the dielectric layer, depositing a tunnel barrier layer over the free layer, and depositing a reference layer over the tunnel barrier layer. The method further includes performing a first patterning process to pattern the plurality of layers, and performing a second patterning process to pattern the reference layer, the tunnel barrier layer, the free layer, and the dielectric layer. The second patterning process stops on a top surface of the spin orbit coupling layer.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: October 11, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wilman Tsai, MingYuan Song, Shy-Jay Lin
  • Patent number: 11456100
    Abstract: Memory stacks, memory devices and method of forming the same are provided. A memory stack includes a spin-orbit torque layer, a magnetic bias layer and a free layer. The magnetic bias layer is in physical contact with the spin-orbit torque layer and has a first magnetic anisotropy. The free layer is disposed adjacent to the spin-orbit torque layer and has a second magnetic anisotropy perpendicular to the first magnetic anisotropy.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: September 27, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Shy-Jay Lin, Wilman Tsai, Ming-Yuan Song
  • Patent number: 11437434
    Abstract: A spin-orbit-torque (SOT) magnetic device includes a bottom metal layer, a first magnetic layer disposed over the bottom metal layer, a spacer layer disposed over the first magnetic layer, and a second magnetic layer disposed over the spacer layer. A diffusion barrier layer for suppressing metal elements of the first magnetic layer from diffusing into the bottom metal layer is disposed between the bottom metal layer and the first magnetic layer.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: September 6, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wilman Tsai, Shy-Jay Lin, Mingyuan Song