Patents by Inventor Wilson Pradeep
Wilson Pradeep has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11933844Abstract: A test override circuit includes a memory that includes multiple memory instances. A path selector receives a control signal from automatic test pattern generator equipment (ATE) to control data access to data paths that are operatively coupled between the memory instances and a plurality of logic endpoints. The path selector generates an output signal that indicates which of the data paths is selected in response to the control signal. A gating circuit enables the selected data paths to be accessed by at least one of the plurality of logic endpoints in response to the output signal from the path selector.Type: GrantFiled: May 26, 2021Date of Patent: March 19, 2024Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Wilson Pradeep, Prakash Narayanan
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Patent number: 11879940Abstract: A circuit includes a multipath memory having multiple cells and a plurality of sequence generators. Each sequence generator of the plurality of sequence generators drives one separate cell of the multiple cells via an automatic test pattern generator (ATPG) mode signal for each cell. The ATPG mode signal for each cell is configured via a sequence configuration input that controls a timing sequence to test each cell. The state of the ATPG mode signal of each cell selects whether test data or functional data is output from the respective cell.Type: GrantFiled: June 23, 2021Date of Patent: January 23, 2024Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Wilson Pradeep, Prakash Narayanan
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Patent number: 11768726Abstract: A circuit includes a dynamic core data register (DCDR) cell that includes a data register, a shift register and an output circuit to route the output state of the data register or the shift register to an output of the DCDR in response to an output control input. A clock gate having a gate control input controls clocking of the shift register in response to a first scan enable signal. An output control gate controls the output control input of the output circuit and controls which outputs from the data register or the shift register are transferred to the output of the output circuit in response to a second scan enable signal. The first scan enable signal and the second scan enable signal to enable a state transition of the shift register at the output of the DCDR.Type: GrantFiled: December 7, 2021Date of Patent: September 26, 2023Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Aravinda Acharya, Wilson Pradeep, Prakash Narayanan
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Publication number: 20230243887Abstract: An integrated circuit for transition fault testing comprises a synchronizing circuit including a first set of shift registers coupled to receive a scan enable signal and to provide a synchronizing signal based on the scan enable signal; a clock leaker circuit coupled to the synchronizing circuit and including a second set of shift registers coupled to receive a first clock signal based on the synchronizing signal and to provide a second clock signal that includes a set of pulses; and a multiplexer (MUX) that includes a first input coupled to receive a shift clock, a second input coupled to the clock leaker circuit to receive the second clock signal, and an output configured to provide an output clock signal that includes a second set of pulses.Type: ApplicationFiled: March 13, 2023Publication date: August 3, 2023Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Wilson Pradeep, Sriraj Chellappan, Shruti Gupta
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Patent number: 11680984Abstract: In some examples, a circuit includes a custom control data register (CCDR) circuit having a scan path. The CCDR circuit includes a shift register and an update register. The shift register is configured to receive scan data from a scan data input (CDR_SCAN_IN) on a first clock edge responsive to a scan enable signal (CDR_SCAN_EN) being enabled. The update register is configured to receive data from the shift register on a second clock edge after the first clock edge when the scan enable (CDR_SCAN_EN) is enabled. The update register data is asserted as a scan data output (CDR_SCAN_OUT). The second scan path includes the scan data input, the shift register, the update register, and the scan data output.Type: GrantFiled: February 28, 2022Date of Patent: June 20, 2023Assignee: Texas Instruments IncorporatedInventors: Wilson Pradeep, Aravinda Acharya, Nikita Naresh
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Patent number: 11604221Abstract: An integrated circuit for transition fault testing comprises a synchronizing circuit including a first set of shift registers coupled to receive a scan enable signal and to provide a synchronizing signal based on the scan enable signal; a clock leaker circuit coupled to the synchronizing circuit and including a second set of shift registers coupled to receive a first clock signal based on the synchronizing signal and to provide a second clock signal that includes a set of pulses; and a multiplexer (MUX) that includes a first input coupled to receive a shift clock, a second input coupled to the clock leaker circuit to receive the second clock signal, and an output configured to provide an output clock signal that includes a second set of pulses.Type: GrantFiled: December 30, 2021Date of Patent: March 14, 2023Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Wilson Pradeep, Sriraj Chellappan, Shruti Gupta
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Patent number: 11519964Abstract: A circuit device is provided with a first codec including a first portion of a logic circuit and a second codec including a second portion of the logic circuit. The circuit device can also include a plurality of first scan chains coupled to the first codec and configured to shift a delayed test vector onto the first codec, wherein the delayed test vector is a test vector with a phase delay. A plurality of second scan chains can be coupled to the second codec and configured to shift the test vector onto the second codec.Type: GrantFiled: June 22, 2021Date of Patent: December 6, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Prakash Narayanan, Wilson Pradeep
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Patent number: 11333707Abstract: Methods for testing an application specific integrated circuit (ASIC). A set of representations is created that overlays power density information and clock gate physical locations of a set of clock gates in a critical sub-chip of the ASIC for test mode power analysis. The set of representations are further grouped in the sub-chip into various groups based on overlapping of the set of representations. Then, a set of test control signals is generated corresponding to each of the set of clock gates during at-speed test mode of operation such that each clock gate with overlapping representations receive different test control signals. Further, patterns are generated using a virtual constraint function to selectively enable the set of test control signals such that the set of test control signals are not activated simultaneously.Type: GrantFiled: December 5, 2019Date of Patent: May 17, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Khushboo Agarwal, Sanjay Krishna Hulical Vijayaraghavachar, Raashid Moin Shaikh, Srivaths Ravi, Wilson Pradeep, Rajesh Kumar Tiwari
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Publication number: 20220091919Abstract: A circuit includes a dynamic core data register (DCDR) cell that includes a data register, a shift register and an output circuit to route the output state of the data register or the shift register to an output of the DCDR in response to an output control input. A clock gate having a gate control input controls clocking of the shift register in response to a first scan enable signal. An output control gate controls the output control input of the output circuit and controls which outputs from the data register or the shift register are transferred to the output of the output circuit in response to a second scan enable signal. The first scan enable signal and the second scan enable signal to enable a state transition of the shift register at the output of the DCDR.Type: ApplicationFiled: December 7, 2021Publication date: March 24, 2022Inventors: Aravinda Acharya, Wilson Pradeep, Prakash Narayanan
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Patent number: 11209481Abstract: A system includes a multiple input signature register (MISR) to receive outputs from M different scan chains in response to N test patterns applied to test an integrated circuit. The MISR provides N test signatures for the integrated circuit based on the outputs of the M different scan chains generated in response to each of the N test patterns. Each of the scan chains holds one or more test data bits that represent behavior of the integrated circuit in response to each of the N test patterns. A shift register is loaded from an interface and holds one of N comparison signatures that is used to validate a respective one of the N test signatures generated according to a given one of the N test patterns. A comparator compares each of the N test signatures with a respective one of the N comparison signatures to determine a failure condition based on the comparison.Type: GrantFiled: December 12, 2018Date of Patent: December 28, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Naman Maheshwari, Wilson Pradeep, Prakash Narayanan
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Patent number: 11194944Abstract: A method that includes disabling circuit paths in a circuit under test during transition fault testing (TFT) of valid timing paths of the circuit under test. The method then tests the circuit paths at slower clock speeds than the clock speed of the valid timing paths during TFT of the circuit paths. Finally, the method tests the circuit paths and the valid timing paths to facilitate testing of the circuit under test.Type: GrantFiled: August 11, 2020Date of Patent: December 7, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Wilson Pradeep, Prakash Narayanan, Saket Jalan
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Patent number: 11194645Abstract: A circuit includes a dynamic core data register (DCDR) cell that includes a data register, a shift register and an output circuit to route the output state of the data register or the shift register to an output of the DCDR in response to an output control input. A clock gate having a gate control input controls clocking of the shift register in response to a first scan enable signal. An output control gate controls the output control input of the output circuit and controls which outputs from the data register or the shift register are transferred to the output of the output circuit in response to a second scan enable signal. The first scan enable signal and the second scan enable signal to enable a state transition of the shift register at the output of the DCDR.Type: GrantFiled: January 8, 2020Date of Patent: December 7, 2021Assignee: Texas Instruments IncorporatedInventors: Aravinda Acharya, Wilson Pradeep, Prakash Narayanan
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Publication number: 20210318378Abstract: A circuit includes a multipath memory having multiple cells and a plurality of sequence generators. Each sequence generator of the plurality of sequence generators drives one separate cell of the multiple cells via an automatic test pattern generator (ATPG) mode signal for each cell. The ATPG mode signal for each cell is configured via a sequence configuration input that controls a timing sequence to test each cell. The state of the ATPG mode signal of each cell selects whether test data or functional data is output from the respective cell.Type: ApplicationFiled: June 23, 2021Publication date: October 14, 2021Inventors: WILSON PRADEEP, PRAKASH NARAYANAN
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Publication number: 20210311121Abstract: A circuit device is provided with a first codec including a first portion of a logic circuit and a second codec including a second portion of the logic circuit. The circuit device can also include a plurality of first scan chains coupled to the first codec and configured to shift a delayed test vector onto the first codec, wherein the delayed test vector is a test vector with a phase delay. A plurality of second scan chains can be coupled to the second codec and configured to shift the test vector onto the second codec.Type: ApplicationFiled: June 22, 2021Publication date: October 7, 2021Inventors: Prakash NARAYANAN, Wilson PRADEEP
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Publication number: 20210278459Abstract: A test override circuit includes a memory that includes multiple memory instances. A path selector receives a control signal from automatic test pattern generator equipment (ATE) to control data access to data paths that are operatively coupled between the memory instances and a plurality of logic endpoints. The path selector generates an output signal that indicates which of the data paths is selected in response to the control signal. A gating circuit enables the selected data paths to be accessed by at least one of the plurality of logic endpoints in response to the output signal from the path selector.Type: ApplicationFiled: May 26, 2021Publication date: September 9, 2021Inventors: WILSON PRADEEP, PRAKASH NARAYANAN
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Patent number: 11073557Abstract: A circuit device is provided with a first codec including a first portion of a logic circuit and a second codec including a second portion of the logic circuit. The circuit device can also include a plurality of first scan chains coupled to the first codec and configured to shift a delayed test vector onto the first codec, wherein the delayed test vector is a test vector with a phase delay. A plurality of second scan chains can be coupled to the second codec and configured to shift the test vector onto the second codec.Type: GrantFiled: May 8, 2019Date of Patent: July 27, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Prakash Narayanan, Wilson Pradeep
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Patent number: 11073553Abstract: A circuit includes a multipath memory having multiple cells and a plurality of sequence generators. Each sequence generator of the plurality of sequence generators drives one separate cell of the multiple cells via an automatic test pattern generator (ATPG) mode signal for each cell. The ATPG mode signal for each cell is configured via a sequence configuration input that controls a timing sequence to test each cell. The state of the ATPG mode signal of each cell selects whether test data or functional data is output from the respective cell.Type: GrantFiled: November 9, 2018Date of Patent: July 27, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Wilson Pradeep, Prakash Narayanan
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Patent number: 11047910Abstract: A test override circuit includes a memory that includes multiple memory instances. A path selector receives a control signal from automatic test pattern generator equipment (ATE) to control data access to data paths that are operatively coupled between the memory instances and a plurality of logic endpoints. The path selector generates an output signal that indicates which of the data paths is selected in response to the control signal. A gating circuit enables the selected data paths to be accessed by at least one of the plurality of logic endpoints in response to the output signal from the path selector.Type: GrantFiled: November 9, 2018Date of Patent: June 29, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Wilson Pradeep, Prakash Narayanan
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Publication number: 20200372197Abstract: A circuit includes a false circuit path in a circuit under test having a starting logic point to an end logic point of the path. The false circuit path is designated as a testing path to be excluded during testing of one or more valid timing paths of the circuit under test. A false path gating circuit gates the starting logic point to the end logic point of the false circuit path. The false path gating circuit disables the false circuit path in response to one or more gating controls asserted during the testing of the one or more valid timing paths of the circuit under test.Type: ApplicationFiled: August 11, 2020Publication date: November 26, 2020Inventors: WILSON PRADEEP, PRAKASH NARAYANAN, SAKET JALAN
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Publication number: 20200355744Abstract: A circuit device is provided with a first codec including a first portion of a logic circuit and a second codec including a second portion of the logic circuit. The circuit device can also include a plurality of first scan chains coupled to the first codec and configured to shift a delayed test vector onto the first codec, wherein the delayed test vector is a test vector with a phase delay. A plurality of second scan chains can be coupled to the second codec and configured to shift the test vector onto the second codec.Type: ApplicationFiled: May 8, 2019Publication date: November 12, 2020Inventors: Prakash NARAYANAN, Wilson PRADEEP