Patents by Inventor Wilson Pradeep
Wilson Pradeep has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10776546Abstract: A circuit includes a false circuit path in a circuit under test having a starting logic point to an end logic point of the path. The false circuit path is designated as a testing path to be excluded during testing of one or more valid timing paths of the circuit under test. A false path gating circuit gates the starting logic point to the end logic point of the false circuit path. The false path gating circuit disables the false circuit path in response to one or more gating controls asserted during the testing of the one or more valid timing paths of the circuit under test.Type: GrantFiled: May 13, 2019Date of Patent: September 15, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Wilson Pradeep, Prakash Narayanan, Saket Jalan
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Publication number: 20200142768Abstract: A circuit includes a dynamic core data register (DCDR) cell that includes a data register, a shift register and an output circuit to route the output state of the data register or the shift register to an output of the DCDR in response to an output control input. A clock gate having a gate control input controls clocking of the shift register in response to a first scan enable signal. An output control gate controls the output control input of the output circuit and controls which outputs from the data register or the shift register are transferred to the output of the output circuit in response to a second scan enable signal. The first scan enable signal and the second scan enable signal to enable a state transition of the shift register at the output of the DCDR.Type: ApplicationFiled: January 8, 2020Publication date: May 7, 2020Inventors: Aravinda Acharya, Wilson Pradeep, Prakash Narayanan
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Publication number: 20200132763Abstract: Methods for testing an application specific integrated circuit (ASIC). A set of representations is created that overlays power density information and clock gate physical locations of a set of clock gates in a critical sub-chip of the ASIC for test mode power analysis. The set of representations are further grouped in the sub-chip into various groups based on overlapping of the set of representations. Then, a set of test control signals is generated corresponding to each of the set of clock gates during at-speed test mode of operation such that each clock gate with overlapping representations receive different test control signals. Further, patterns are generated using a virtual constraint function to selectively enable the set of test control signals such that the set of test control signals are not activated simultaneously.Type: ApplicationFiled: December 5, 2019Publication date: April 30, 2020Applicant: Texas Instruments IncorporatedInventors: Khushboo Agarwal, Sanjay Krishna Hulical Vijayaraghavachar, Raashid Moin Shaikh, Srivaths Ravi, Wilson Pradeep, Rajesh Kumar Tiwari
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Patent number: 10579454Abstract: A circuit includes a dynamic core data register (DCDR) cell that includes a data register, a shift register and an output circuit to route the output state of the data register or the shift register to an output of the DCDR in response to an output control input. A clock gate having a gate control input controls clocking of the shift register in response to a first scan enable signal. An output control gate controls the output control input of the output circuit and controls which outputs from the data register or the shift register are transferred to the output of the output circuit in response to a second scan enable signal. The first scan enable signal and the second scan enable signal to enable a state transition of the shift register at the output of the DCDR.Type: GrantFiled: June 22, 2017Date of Patent: March 3, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Aravinda Acharya, Wilson Pradeep, Prakash Narayanan
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Patent number: 10473717Abstract: Described examples include a method of providing K bits of test data to a combinatorial circuit. The method further includes generating N bits of test data using the combinatorial circuit, where N is greater than K. The method further includes providing the N bits of test data to a module under test.Type: GrantFiled: November 9, 2016Date of Patent: November 12, 2019Assignee: TEXAS INSTRUMENTS INCORPORATEDInventor: Wilson Pradeep
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Publication number: 20190266303Abstract: A circuit includes a false circuit path in a circuit under test having a starting logic point to an end logic point of the path. The false circuit path is designated as a testing path to be excluded during testing of one or more valid timing paths of the circuit under test. A false path gating circuit gates the starting logic point to the end logic point of the false circuit path. The false path gating circuit disables the false circuit path in response to one or more gating controls asserted during the testing of the one or more valid timing paths of the circuit under test.Type: ApplicationFiled: May 13, 2019Publication date: August 29, 2019Inventors: WILSON PRADEEP, PRAKASH NARAYANAN, SAKET JALAN
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Publication number: 20190204382Abstract: A test override circuit includes a memory that includes multiple memory instances. A path selector receives a control signal from automatic test pattern generator equipment (ATE) to control data access to data paths that are operatively coupled between the memory instances and a plurality of logic endpoints. The path selector generates an output signal that indicates which of the data paths is selected in response to the control signal. A gating circuit enables the selected data paths to be accessed by at least one of the plurality of logic endpoints in response to the output signal from the path selector.Type: ApplicationFiled: November 9, 2018Publication date: July 4, 2019Inventors: WILSON PRADEEP, PRAKASH NARAYANAN
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Publication number: 20190206507Abstract: A circuit includes a multipath memory having multiple cells and a plurality of sequence generators. Each sequence generator of the plurality of sequence generators drives one separate cell of the multiple cells via an automatic test pattern generator (ATPG) mode signal for each cell. The ATPG mode signal for each cell is configured via a sequence configuration input that controls a timing sequence to test each cell. The state of the ATPG mode signal of each cell selects whether test data or functional data is output from the respective cell.Type: ApplicationFiled: November 9, 2018Publication date: July 4, 2019Inventors: WILSON PRADEEP, PRAKASH NARAYANAN
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Patent number: 10331826Abstract: A circuit includes a false circuit path in a circuit under test having a starting logic point to an end logic point of the path. The false circuit path is designated as a testing path to be excluded during testing of one or more valid timing paths of the circuit under test. A false path gating circuit gates the starting logic point to the end logic point of the false circuit path. The false path gating circuit disables the false circuit path in response to one or more gating controls asserted during the testing of the one or more valid timing paths of the circuit under test.Type: GrantFiled: June 22, 2017Date of Patent: June 25, 2019Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Wilson Pradeep, Prakash Narayanan, Saket Jalan
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Publication number: 20190113566Abstract: A system includes a multiple input signature register (MISR) to receive outputs from M different scan chains in response to N test patterns applied to test an integrated circuit. The MISR provides N test signatures for the integrated circuit based on the outputs of the M different scan chains generated in response to each of the N test patterns. Each of the scan chains holds one or more test data bits that represent behavior of the integrated circuit in response to each of the N test patterns. A shift register is loaded from an interface and holds one of N comparison signatures that is used to validate a respective one of the N test signatures generated according to a given one of the N test patterns. A comparator compares each of the N test signatures with a respective one of the N comparison signatures to determine a failure condition based on the comparison.Type: ApplicationFiled: December 12, 2018Publication date: April 18, 2019Inventors: NAMAN MAHESHWARI, WILSON PRADEEP, PRAKASH NARAYANAN
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Patent number: 10184980Abstract: A system includes a multiple input signature register (MISR) to receive outputs from M different scan chains in response to N test patterns applied to test an integrated circuit. The MISR provides N test signatures for the integrated circuit based on the outputs of the M different scan chains generated in response to each of the N test patterns. Each of the scan chains holds one or more test data bits that represent behavior of the integrated circuit in response to each of the N test patterns. A shift register is loaded from an interface and holds one of N comparison signatures that is used to validate a respective one of the N test signatures generated according to a given one of the N test patterns. A comparator compares each of the N test signatures with a respective one of the N comparison signatures to determine a failure condition based on the comparison.Type: GrantFiled: December 30, 2016Date of Patent: January 22, 2019Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Naman Maheshwari, Wilson Pradeep, Prakash Narayanan
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Publication number: 20180307553Abstract: A circuit includes a dynamic core data register (DCDR) cell that includes a data register, a shift register and an output circuit to route the output state of the data register or the shift register to an output of the DCDR in response to an output control input. A clock gate having a gate control input controls clocking of the shift register in response to a first scan enable signal. An output control gate controls the output control input of the output circuit and controls which outputs from the data register or the shift register are transferred to the output of the output circuit in response to a second scan enable signal. The first scan enable signal and the second scan enable signal to enable a state transition of the shift register at the output of the DCDR.Type: ApplicationFiled: June 22, 2017Publication date: October 25, 2018Inventors: ARAVINDA ACHARYA, WILSON PRADEEP, PRAKASH NARAYANAN
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Publication number: 20180307788Abstract: A circuit includes a false circuit path in a circuit under test having a starting logic point to an end logic point of the path. The false circuit path is designated as a testing path to be excluded during testing of one or more valid timing paths of the circuit under test. A false path gating circuit gates the starting logic point to the end logic point of the false circuit path. The false path gating circuit disables the false circuit path in response to one or more gating controls asserted during the testing of the one or more valid timing paths of the circuit under test.Type: ApplicationFiled: June 22, 2017Publication date: October 25, 2018Inventors: WILSON PRADEEP, PRAKASH NARAYANAN, SAKET JALAN
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Publication number: 20180128877Abstract: Described examples include a method of providing K bits of test data to a combinatorial circuit. The method further includes generating N bits of test data using the combinatorial circuit, where N is greater than K. The method further includes providing the N bits of test data to a module under test.Type: ApplicationFiled: November 9, 2016Publication date: May 10, 2018Inventor: Wilson Pradeep
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Publication number: 20180067164Abstract: A system includes a multiple input signature register (MISR) to receive outputs from M different scan chains in response to N test patterns applied to test an integrated circuit. The MISR provides N test signatures for the integrated circuit based on the outputs of the M different scan chains generated in response to each of the N test patterns. Each of the scan chains holds one or more test data bits that represent behavior of the integrated circuit in response to each of the N test patterns. A shift register is loaded from an interface and holds one of N comparison signatures that is used to validate a respective one of the N test signatures generated according to a given one of the N test patterns. A comparator compares each of the N test signatures with a respective one of the N comparison signatures to determine a failure condition based on the comparison.Type: ApplicationFiled: December 30, 2016Publication date: March 8, 2018Inventors: NAMAN MAHESHWARI, WILSON PRADEEP, PRAKASH NARAYANAN
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Patent number: 9535123Abstract: A scan chain may be formed throughout an integrated circuit in which the scan chain includes at least a first segment and a second segment. A first portion of a test pattern is scanned into the first segment by clocking a first scan cell of the first segment with an even clock while clocking a remainder of the plurality of scan cells in the first segment with an odd clock, in which the odd clock is out of phase with the even clock, in which the even clock and odd clock have a rate equal to a scan rate of the test pattern divided by an integer N. A second portion of the test pattern is scanned into the second segment by clocking the plurality of scan cells in the second segment with the odd clock, such that the second portion of the test pattern is not scanned into the first segment.Type: GrantFiled: December 31, 2015Date of Patent: January 3, 2017Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Rajesh Kumar Mittal, Wilson Pradeep, Vivek Singhal
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Publication number: 20160266202Abstract: A scan chain may be formed throughout an integrated circuit in which the scan chain includes at least a first segment and a second segment. A first portion of a test pattern is scanned into the first segment by clocking a first scan cell of the first segment with an even clock while clocking a remainder of the plurality of scan cells in the first segment with an odd clock, in which the odd clock is out of phase with the even clock, in which the even clock and odd clock have a rate equal to a scan rate of the test pattern divided by an integer N. A second portion of the test pattern is scanned into the second segment by clocking the plurality of scan cells in the second segment with the odd clock, such that the second portion of the test pattern is not scanned into the first segment.Type: ApplicationFiled: December 31, 2015Publication date: September 15, 2016Inventors: Rajesh Kumar Mittal, Wilson Pradeep, Vivek Singhal
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Publication number: 20150212152Abstract: Methods for testing an application specific integrated circuit (ASIC). A set of representations is created that overlays power density information and clock gate physical locations of a set of clock gates in a critical sub-chip of the ASIC for test mode power analysis. The set of representations are further grouped in the sub-chip into various groups based on overlapping of the set of representations. Then, a set of test control signals is generated corresponding to each of the set of clock gates during at-speed test mode of operation such that each clock gate with overlapping representations receive different test control signals. Further, patterns are generated using a virtual constraint function to selectively enable the set of test control signals such that the set of test control signals are not activated simultaneously.Type: ApplicationFiled: January 26, 2015Publication date: July 30, 2015Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Khushboo Agarwal, Sanjay Krishna H V, Raashid Moin Shaikh, Srivaths Ravi, Wilson Pradeep, Rajesh Kumar Tiwari