Patents by Inventor Wim Dehaene
Wim Dehaene has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11799563Abstract: A method of generating ultrasound by driving an array of ultrasonic transducers comprises a charge transfer procedure. The charge transfer procedure comprises switching a terminal of a first ultrasonic transducer of the array, at a first electric potential, to a charge distribution bus; switching a terminal of a second ultrasonic transducer of the array, at a second electric potential different than the first potential, to the charge distribution bus; and allowing charge to flow between the first ultrasonic transducer and the second ultrasonic transducer through the charge distribution bus.Type: GrantFiled: March 23, 2021Date of Patent: October 24, 2023Assignees: Imec vzw, Katholieke Universiteit LeuvenInventors: Jonas Pelgrims, Kris Myny, Wim Dehaene
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Patent number: 11645503Abstract: A circuit is provided. The circuit includes a sampling circuit connectable to a multibit memory array and that samples a voltage across a sampling capacitor, a capacitance network including a plurality of capacitors and switching elements such that the capacitance network has a capacitance that depends on the configuration of the switching elements, and a buffering circuit configured to charge the capacitance of the capacitance network based on the voltage across the sampling capacitor. The circuit is configured to operate the capacitance network in a first state and a second state, wherein the capacitance in the states depends on an input value to the circuit. The circuit is also configured to charge the capacitance network in the first state and to allow the charge to redistribute within the capacitance network when it changes from the first to the second state. A system and method including such circuits are also provided.Type: GrantFiled: December 20, 2019Date of Patent: May 9, 2023Assignees: Imec vzw, Katholieke Universiteit LeuvenInventors: Mohit Gupta, Bharani Chakravarthy Chava, Wim Dehaene, Sushil Sakhare
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Publication number: 20220349749Abstract: A charge sensor element includes a charge collecting detector configured to generate an intensity signal indicative of an amount of charge at an internal charge sensor element node, an amplifier transistor that is electrically connected to the internal charge sensor element node and configured to amplify the intensity signal, and a reset transistor that is electrically connected to the internal charge sensor element node and configured to reset the intensity signal. The amplifier transistor or the reset transistor includes a front gate and a back gate that are configured to control the amplifier transistor or the reset transistor.Type: ApplicationFiled: April 19, 2022Publication date: November 3, 2022Inventors: Aris Siskos, Florian De Roose, Kris Myny, Wim Dehaene
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Publication number: 20220199002Abstract: A compensated current mirror circuit comprises a current mirror with a primary current path and a secondary current path, configured to mirror a current through the primary current path to the secondary current path. The current is settable by switching a reference current through a reference current line into the primary current path. A primary current mirror transistor is connected in series with the primary current path. A secondary current mirror transistor is connected in series with the secondary current path. A gate of the primary current mirror transistor is connected to a gate of the secondary current mirror transistor at a current mirror node. A compensation block is connected to a back gate of the secondary current mirror transistor and to one or more compensation control lines, and is configured to apply a compensation signal at the back gate based on the compensation control lines.Type: ApplicationFiled: December 17, 2021Publication date: June 23, 2022Inventors: Lynn Verschueren, Kris Myny, Jan Genoe, Wim Dehaene
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Publication number: 20220201821Abstract: A pixel circuit for driving a light-emitting diode (LED) comprises a current-mirror, comprising a primary current path and a secondary current path, arranged to mirror a current through the primary current path to the secondary current path. The current through the primary current path is settable by switching a reference current into the primary current path through a reference current line. The secondary current path is configured to drive the LED. The pixel circuit also includes a switch component arranged to switch the LED to and from the secondary current path based on one or more switch control lines.Type: ApplicationFiled: December 9, 2021Publication date: June 23, 2022Inventors: Lynn Verschueren, Kris Myny, Jan Genoe, Wim Dehaene, Wim Van Eessen, Patrick Willem
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Publication number: 20210382518Abstract: An integrated circuit and method of designing an integrated circuit including an error detection and correction circuit is described. The integrated circuit includes a data-path being arranged between an output of a first register and second register clocked by a system clock. The integrated circuit includes a timing error detection and correction circuit (EDAC) which has a clock unit configured to receive a reference clock and to provide a delayed reference clock. The EDAC includes a plurality of transition detectors coupled to a respective node on the data-path and an error detection circuit coupled to each transition detector. The error detection circuit flags an error if a transition occurs during a time period between a transition of the reference clock and a corresponding transition of the delayed reference clock. A timing correction circuit coupled to the error detection circuit outputs the system clock derived from the delayed reference clock.Type: ApplicationFiled: June 1, 2021Publication date: December 9, 2021Inventors: Roel Lieve P Uytterhoeven, Wim Dehaene
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Publication number: 20210306079Abstract: A method of generating ultrasound by driving an array of ultrasonic transducers comprises a charge transfer procedure. The charge transfer procedure comprises switching a terminal of a first ultrasonic transducer of the array, at a first electric potential, to a charge distribution bus; switching a terminal of a second ultrasonic transducer of the array, at a second electric potential different than the first potential, to the charge distribution bus; and allowing charge to flow between the first ultrasonic transducer and the second ultrasonic transducer through the charge distribution bus.Type: ApplicationFiled: March 23, 2021Publication date: September 30, 2021Inventors: Jonas Pelgrims, Kris Myny, Wim Dehaene
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Patent number: 10978000Abstract: A method for driving an active matrix display comprising a plurality of pixels, wherein each pixel comprises a drive transistor having a driver gate, is disclosed. The method comprises: receiving information of a desired image to be displayed; determining a compensated voltage for the driver gate for each pixel based on calibration data, wherein the calibration data comprises a set of individual calibration values applying to different pixels, and wherein the compensated voltage compensates for differences between pixels affecting a relation of an intensity of light output by the pixel as function of a difference between the voltage applied to the driver gate and a threshold voltage of the drive transistor; and outputting the compensated voltage for the driver gate for each of the pixels.Type: GrantFiled: May 16, 2019Date of Patent: April 13, 2021Assignee: IMEC vzwInventors: Lynn Verschueren, Kris Myny, Jan Genoe, Wim Dehaene
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Publication number: 20200210822Abstract: A circuit is provided. The circuit includes a sampling circuit connectable to a multibit memory array and that samples a voltage across a sampling capacitor, a capacitance network including a plurality of capacitors and switching elements such that the capacitance network has a capacitance that depends on the configuration of the switching elements, and a buffering circuit configured to charge the capacitance of the capacitance network based on the voltage across the sampling capacitor. The circuit is configured to operate the capacitance network in a first state and a second state, wherein the capacitance in the states depends on an input value to the circuit. The circuit is also configured to charge the capacitance network in the first state and to allow the charge to redistribute within the capacitance network when it changes from the first to the second state. A system and method including such circuits are also provided.Type: ApplicationFiled: December 20, 2019Publication date: July 2, 2020Inventors: Mohit Gupta, Bharani Chakravarthy Chava, Wim Dehaene, Sushil Sakhare
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Publication number: 20190355308Abstract: A method for driving an active matrix display comprising a plurality of pixels, wherein each pixel comprises a drive transistor having a driver gate, is disclosed. The method comprises: receiving information of a desired image to be displayed; determining a compensated voltage for the driver gate for each pixel based on calibration data, wherein the calibration data comprises a set of individual calibration values applying to different pixels, and wherein the compensated voltage compensates for differences between pixels affecting a relation of an intensity of light output by the pixel as function of a difference between the voltage applied to the driver gate and a threshold voltage of the drive transistor; and outputting the compensated voltage for the driver gate for each of the pixels.Type: ApplicationFiled: May 16, 2019Publication date: November 21, 2019Inventors: Lynn Verschueren, Kris Myny, Jan Genoe, Wim Dehaene
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Patent number: 10429322Abstract: The present invention relates to a millimeter or terahertz wave sensor for providing inline inspection, preferably including but not limited to continuous monitoring of objects, for example thin sheet dielectric material.Type: GrantFiled: June 13, 2016Date of Patent: October 1, 2019Assignee: HAMMER-IMSInventors: Noël Deferm, Tom Redant, Wim Dehaene, Patrick Reynaert
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Publication number: 20190205095Abstract: A semiconductor cell comprising a memory element for storing a first binary operand is disclosed. In one aspect, the memory element provides complementary memory outputs, and a multiplication block that is locally and uniquely associated with the memory element. The multiplication block may be configured to receive complementary input signals representing binary input data and the complementary memory outputs of the associated memory element representing the first binary operand, implement a multiplication operation on these signals, and provide an output of the multiplication operation to an output port. An array of semiconductor cells and a neural network circuit comprising such array are also disclosed.Type: ApplicationFiled: December 17, 2018Publication date: July 4, 2019Inventors: Mohit Gupta, Wim Dehaene, Sushil Sakhare, Pieter Weckx
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Publication number: 20180180557Abstract: The present invention relates to a millimeter or terahertz wave sensor for providing inline inspection, preferably including but not limited to continuous monitoring of objects, for example thin sheet dielectric material.Type: ApplicationFiled: June 13, 2016Publication date: June 28, 2018Inventors: Noël DEFERM, Tom REDANT, Wim DEHAENE, Patrick REYNAERT
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Patent number: 8958238Abstract: A memory device having complementary global and local bit-lines, the complementary local bit-lines being connectable to the complementary global bit-lines by means of a local write receiver which is configured for creating a full voltage swing on the complementary local bit lines from a reduced voltage swing on the complementary global bit lines. The local write receiver comprises a connection mechanism for connecting the local to the global bit-lines and a pair of cross-coupled inverters directly connected to the complementary local bit lines for converting the reduced voltage swing to the full voltage swing on the complementary local bit lines.Type: GrantFiled: August 30, 2013Date of Patent: February 17, 2015Assignees: Stichting IMEC Nederland, Kathoieke Universiteit LeuvenInventors: Vibhu Sharma, Stefan Cosemans, Wim Dehaene, Francky Catthoor, Maryam Ashouei, Jos Huisken
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Publication number: 20140071737Abstract: A memory device having complementary global and local bit-lines, the complementary local bit-lines being connectable to the complementary global bit-lines by means of a local write receiver which is configured for creating a full voltage swing on the complementary local bit lines from a reduced voltage swing on the complementary global bit lines. The local write receiver comprises a connection mechanism for connecting the local to the global bit-lines and a pair of cross-coupled inverters directly connected to the complementary local bit lines for converting the reduced voltage swing to the full voltage swing on the complementary local bit lines.Type: ApplicationFiled: August 30, 2013Publication date: March 13, 2014Applicants: Katholieke Universiteit Leuven, Stichting IMEC NederlandInventors: Vibhu Sharma, Stefan Cosemans, Wim Dehaene, Francky Catthoor, Maryam Ashouei, Jos Huisken
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Patent number: 8576614Abstract: A tunnel transistor is provided including a drain, a source and at least a first gate for controlling current between the drain and the source, wherein the first sides of respectively the first and the second gate dielectric material are positioned substantially along and substantially contact respectively the first and the second semiconductor part.Type: GrantFiled: August 16, 2012Date of Patent: November 5, 2013Assignees: IMEC, Katholieke Universiteit Leuven, K.U. Leuven R&DInventors: Marc Heyns, Cedric Huyghebaert, Anne S. Verhulst, Daniele Leonelli, Rita Rooyackers, Wim Dehaene
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Patent number: 8462572Abstract: An ultra low power sense amplifier circuit for amplifying a low swing input signal to a full swing output signal is disclosed. In one aspect, the amplifier circuit includes a first amplifier stage for pre-amplifying the input signal to an intermediate signal on its internal nodes, a second amplifier stage for amplifying the intermediate signal to the output signal, and a control circuit for sequentially activating the first and second amplifier. The first amplifier has a capacitor for limiting energy consumption and two upsized PMOS transistors without NMOS transistors.Type: GrantFiled: September 13, 2011Date of Patent: June 11, 2013Assignees: Stichting IMEC Nederland, Katholieke Universiteit LeuvenInventors: Vibhu Sharma, Stefan Cosemans, Wim Dehaene, Francky Catthoor, Maryam Ashouei, Jos Huisken
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Patent number: 8451156Abstract: This disclosure relates to analog to digital conversion using irregular sampling. A method may include combining an analog signal with a feedback signal into a combined signal, filtering the combined signal using a digital noise shaping filter into a combined noise shaped signal, modulating the combined noise shaped signal into a modulated signal, generating samples of the modulated signal, and reconstructing as a digital signal the analog signal from the samples of the modulated signal.Type: GrantFiled: November 27, 2010Date of Patent: May 28, 2013Assignee: Infineon Technologies AGInventors: Jorg Daniels, Wim Dehaene, Andreas Wiesbauer
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Publication number: 20130064005Abstract: A tunnel transistor is provided comprising a drain, a source and at least a first gate for controlling current between the drain and the source, wherein the first sides of respectively the first and the second gate dielectric material are positioned substantially along and substantially contact respectively the first and the second semiconductor part.Type: ApplicationFiled: August 16, 2012Publication date: March 14, 2013Applicants: Katholieke Universiteit Leuven, K.U. LEUVEN R&D, IMECInventors: Marc Heyns, Cedric Huyghebaert, Anne S. Verhulst, Daniele Leonelli, Rita Rooyackers, Wim Dehaene
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Publication number: 20120063211Abstract: A method for improving writability of an SRAM cell is disclosed. In one aspect, the method includes applying a first voltage higher than the global ground voltage and a third voltage higher than the global supply voltage to the ground supply nodes of the invertors of the SRAM cell, pre-charging one of the complementary bitlines to the global ground voltage, and applying a second voltage higher than the global supply voltage to the access transistors during a write operation to the SRAM cell.Type: ApplicationFiled: September 13, 2011Publication date: March 15, 2012Applicants: IMEC, Katholieke Universiteit Leuven, Stichting IMEC NederlandInventors: Vibhu Sharma, Stefan Cosemans, Wim Dehaene, Francky Catthoor, Maryan Ashouei, Jos Huisken