Abstract: A method for improving writability of an SRAM cell is disclosed. In one aspect, the method includes applying a first voltage higher than the global ground voltage and a third voltage higher than the global supply voltage to the ground supply nodes of the invertors of the SRAM cell, pre-charging one of the complementary bitlines to the global ground voltage, and applying a second voltage higher than the global supply voltage to the access transistors during a write operation to the SRAM cell.

Abstract: An ultra low power sense amplifier circuit for amplifying a low swing input signal to a full swing output signal is disclosed. In one aspect, the amplifier circuit includes a first amplifier stage for pre-amplifying the input signal to an intermediate signal on its internal nodes, a second amplifier stage for amplifying the intermediate signal to the output signal, and a control circuit for sequentially activating the first and second amplifier. The first amplifier has a capacitor for limiting energy consumption and two upsized PMOS transistors without NMOS transistors.

Abstract: An apparatus is provided which has a first analog input and a second analog input. In a particular implementation, the first analog input is coupled to a first controllable oscillator and the second analog input is coupled to a second controllable oscillator. First and second digital output signals generated based on output oscillations from the first controllable oscillator and the second controllable oscillator are combined.

Abstract: A semiconductor memory device is disclosed. In one aspect, the device includes memory blocks with memory cells connected to a local bit-line, each local bit-line being connectable to a global bit-line for memory readout. There are also pre-charging circuitry for pre-charging the bit-lines and a read buffer for discharging the global bit-line during a read operation. The local bit-lines are pre-charged to a predetermined first voltage substantially lower than the supply voltage (VDD) of the memory device. A segment buffer is provided between each local bit-line and an input node of the respective read buffer. The segment buffer activates the read buffer during the read operation upon occurrence of a discharge on the connected local bit-line.

Abstract: An apparatus is provided which has a first analog input and a second analog input. In a particular implementation, the first analog input is coupled to a first controllable oscillator and the second analog input is coupled to a second controllable oscillator. First and second digital output signals generated based on output oscillations from the first controllable oscillator and the second controllable oscillator are combined.

Abstract: This disclosure relates to analog to digital conversion using irregular sampling. A method may include combining an analog signal with a feedback signal into a combined signal, filtering the combined signal using a digital noise shaping filter into a combined noise shaped signal, modulating the combined noise shaped signal into a modulated signal, generating samples of the modulated signal, and reconstructing as a digital signal the analog signal from the samples of the modulated signal.

Abstract: A memory circuit with multi-sized sense amplifier redundancy is disclosed. In one aspect, the circuit includes sense amplifiers connected to differential bit-lines and configured to amplify a voltage difference sensed on the differential bit-lines. The sense amplifiers include a first set of smaller sense amplifiers and a second set of larger sense amplifiers redundantly arranged to the first set to form redundant groups which each contain one smaller sense amplifiers and one larger sense amplifiers. The larger sense amplifiers have a failure rate lower than the smaller sense amplifiers. The circuit also includes calibration circuitry connected to enable and disable nodes of each of the sense amplifiers and configured to select for each redundant group either the smaller sense amplifier of the first set or, if the smaller sense amplifier fails, the larger sense amplifier of the second set.

Abstract: This disclosure relates to analog to digital conversion using irregular sampling.

Abstract: Disclosed herein are memory devices comprising a plurality of memory cells to which a standby voltage is to be supplied during standby mode to avoid loss of data, and methods of operating said memory devices, the methods comprising: (a) determining an actual value of a bit integrity parameter of the memory cells; (b) comparing said actual value with a predetermined minimal value of the bit integrity parameter which takes into account possible variations in cell properties as a result of process variations; and (c) adjusting the standby voltage towards a more optimal value based on the result of the comparison in such a way that said bit integrity parameter determined for said more optimal value of the standby voltage approaches the predetermined minimal value. The circuitry for measuring the bit integrity parameter preferably comprises a plurality of replica test cells which are added to the memory matrix.

Abstract: A regulator circuit receives a power supply and provides a regulated power supply output suitable for integrated circuitry. It has a controllable current source circuit, a controller and a capacitor, such that an output of the controllable current source circuit can provide a lower frequency current part of the regulated power supply output, and the capacitor can supply a higher frequency current part of the regulated power supply output. The controllable current source circuit is controlled according to feedback from the regulated power supply output, and to restrict a rate of change of the output of the controllable current source circuit. The amount of EMI noise caused by high rate of change of current in power supply lines to the regulator circuit can be reduced. This can be done more efficiently or using a smaller capacitor than known arrangements.

Abstract: A multiple output time-to-digital converter (TDC) and an Analog-to-Digital Converter (ADC) incorporating the multiple output TDC is disclosed.

Abstract: A multiple output time-to-digital converter (TDC) and an Analog-to-Digital Converter (ADC) incorporating the multiple output TDC is dislosed.

Abstract: This disclosure relates to analog to digital conversion using irregular sampling.

Abstract: Disclosed herein are memory devices comprising a plurality of memory cells to which a standby voltage is to be supplied during standby mode to avoid loss of data, and methods of operating said memory devices, the methods comprising: (a) determining an actual value of a bit integrity parameter of the memory cells; (b) comparing said actual value with a predetermined minimal value of the bit integrity parameter which takes into account possible variations in cell properties as a result of process variations; and (c) adjusting the standby voltage towards a more optimal value based on the result of the comparison in such a way that said bit integrity parameter determined for said more optimal value of the standby voltage approaches the predetermined minimal value. The circuitry for measuring the bit integrity parameter preferably comprises a plurality of replica test cells which are added to the memory matrix.

Abstract: A regulator circuit receives a power supply and provides a regulated power supply output suitable for integrated circuitry. It has a controllable current source circuit, a controller and a capacitor, such that an output of the controllable current source circuit can provide a lower frequency current part of the regulated power supply output, and the capacitor can supply a higher frequency current part of the regulated power supply output. The controllable current source circuit is controlled according to feedback from the regulated power supply output, and to restrict a rate of change of the output of the controllable current source circuit. The amount of EMI noise caused by high rate of change of current in power supply lines to the regulator circuit can be reduced. This can be done more efficiently or using a smaller capacitor than known arrangements.

Abstract: A receiver and a method for receiving a signal including a carrier modulated with a known training sequence is described in which an estimate a carrier frequency offset is obtained from an autocorrelation signal by autocorrelation of the part of the received signal containing a known training sequence. The received signal is compensated with the frequency offset obtained to form a compensated received signal, and a timing reference for the received signal is obtained by cross-correlation of the compensated received signal with a known training sequence.

Abstract: A receiver and a method for receiving a signal comprising a carrier modulated with a known training sequence is described in which an estimate a carrier frequency offset is obtained from an autocorrelation signal by autocorrelation of the part of the received signal containing a known training sequence. The received signal is compensated with the frequency offset obtained to form a compensated received signal, and a timing reference for the received signal is obtained by cross-correlation of the compensated received signal with a known training sequence.

Abstract: A receiver and a method for receiving a signal comprising a carrier modulated with a known training sequence is described in which an estimate a carrier frequency offset is obtained from an autocorrelation signal by autocorrelation of the part of the received signal containing a known training sequence. The received signal is compensated with the frequency offset obtained to form a compensated received signal, and a timing reference for the received signal is obtained by cross-correlation of the compensated received signal with a known training sequence.

Abstract: A servo system for controlling the position of a read/write head in a disk drive is provided. The servo system includes two input terminals for sequentially receiving a plurality of input signal AC voltage bursts of a burst pattern, wherein the input signal bursts include positional information of the head. Demodulation circuitry, coupled to the input terminals, sequentially demodulates each input signal burst and provides a demodulated signal for each burst. The demodulation circuitry includes translation circuitry, coupled to the input, for sequentially translating each input voltage burst to a translated current. A rectifier circuit, coupled to the translation circuitry, including an absolute value circuit and a current mirror circuit, sequentially rectifies each translated current and produces a driving signal. An integrator, coupled to the rectifier circuit, sequentially integrates each driving signal. The integrator includes an integration capacitor which is sequentially charged by each driving signal.