Patents by Inventor Winfried Kaindl
Winfried Kaindl has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11869966Abstract: A method includes forming a trench in a first surface in an edge region of a semiconductor body, forming a plurality of superjunction transistor cells in an inner region of a semiconductor body, and forming an insulation layer on the first surface of the semiconductor body in the edge region and in the inner region, wherein forming the insulation layer includes a thermal oxidation process.Type: GrantFiled: November 17, 2021Date of Patent: January 9, 2024Assignee: Infineon Technologies Austria AGInventors: Hans Weber, Christian Fachmann, Franz Hirler, Winfried Kaindl, Markus Rochel
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Publication number: 20230344422Abstract: A method is disclosed. The method includes switching off a power transistor circuit in an electronic circuit. The electronic circuit includes a power source and a load circuit. The power transistor circuit is connected between the power source and the load circuit. Switching off the power transistor circuit includes operating at least one power transistor included in the power transistor circuit in an Avalanche mode so that at least a portion of energy stored in the electronic circuit before switching off the power transistor circuit is dissipated in the at least one power transistor.Type: ApplicationFiled: April 4, 2023Publication date: October 26, 2023Inventors: Christian Fachmann, Matteo-Alessandro Kutschak, Otto Wiedenbauer, Winfried Kaindl, Hans Weber
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Patent number: 11508841Abstract: A semiconductor device includes a semiconductor body having a first surface and second surface opposite to the first surface in a vertical direction, and a plurality of transistor cells at least partly integrated in the semiconductor body. Each transistor cell includes at least two source regions, first and second gate electrodes spaced apart from each other in a first horizontal direction and arranged adjacent to and dielectrically insulated from a continuous body region, a drift region separated from the at least two source regions by the body region, and at least three contact plugs extending from the body region towards a source electrode in the vertical direction. The at least three contact plugs are arranged successively between the first and second gate electrodes. Only the two outermost contact plugs that are arranged closest to the first and second gate electrodes, respectively, directly adjoin at least one of the source regions.Type: GrantFiled: June 4, 2020Date of Patent: November 22, 2022Assignee: Infineon Technologies Dresden GmbH & Co. KGInventors: Franz Hirler, Christian Fachmann, Winfried Kaindl, Hans Weber
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Patent number: 11374125Abstract: A transistor device includes transistor cells each having source and drift regions of a first doping type and a body region of a second doping type in a first region of a semiconductor body, and a gate electrode dielectrically insulated from the body region. A gate conductor arranged on top of a second region of the semiconductor body is electrically connected to each gate electrode. A source conductor arranged on top of the first region is connected to each source and body region. A discharging region of the second doping type is arranged in the second region and located at least partially below the gate conductor, and includes at least one lower dose section in which a doping dose is lower than a minimum doping dose in other sections of the discharging region. The at least one lower dose section is associated with a corner of the gate conductor.Type: GrantFiled: March 19, 2020Date of Patent: June 28, 2022Assignee: Infineon Technologies Austria AGInventors: Winfried Kaindl, Gabor Mezoesi, Enrique Vecino Vazquez
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Publication number: 20220077309Abstract: A method includes forming a trench in a first surface in an edge region of a semiconductor body, forming a plurality of superjunction transistor cells in an inner region of a semiconductor body, and forming an insulation layer on the first surface of the semiconductor body in the edge region and in the inner region, wherein forming the insulation layer includes a thermal oxidation process.Type: ApplicationFiled: November 17, 2021Publication date: March 10, 2022Inventors: Hans Weber, Christian Fachmann, Franz Hirler, Winfried Kaindl, Markus Rochel
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Patent number: 11211483Abstract: A method and a transistor device are disclosed. The method includes: forming a trench in a first surface in an edge region of a semiconductor body; forming an insulation layer in the trench and on the first surface of the semiconductor body; and planarizing the insulation layer so that a trench insulation layer that fills the trench remains, wherein forming the insulation layer comprises a thermal oxidation process.Type: GrantFiled: September 30, 2019Date of Patent: December 28, 2021Assignee: Infineon Technologies Austria AGInventors: Hans Weber, Christian Fachmann, Franz Hirler, Winfried Kaindl, Markus Rochel
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Patent number: 10943987Abstract: A transistor device includes at least one transistor cell, having, in a semiconductor body, a source region of a first doping type in a body region of a second doping type, a drain region, and a drift region of the first doping type adjoining the body region and arranged between the body region and the drain region. A low-resistance region of the second doping type in the body region adjoins the source region. A gate electrode dielectrically insulated from the source and body regions by a gate dielectric is arranged above a first surface of the semiconductor body. A length of an overlap between the source region and the gate electrode is larger than 70 nanometers. A doping profile of the low-resistance region along a line that is vertical to the first surface and goes through an edge of the gate electrode has a maximum of higher than 1E19 cm?3.Type: GrantFiled: June 25, 2019Date of Patent: March 9, 2021Assignee: Infineon Technologies Austria AGInventors: Katarzyna Kowalik-Seidl, Bjoern Fischer, Winfried Kaindl, Markus Schmitt, Matthias Wegscheider
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Publication number: 20200388703Abstract: A semiconductor device includes a semiconductor body having a first surface and second surface opposite to the first surface in a vertical direction, and a plurality of transistor cells at least partly integrated in the semiconductor body. Each transistor cell includes at least two source regions, first and second gate electrodes spaced apart from each other in a first horizontal direction and arranged adjacent to and dielectrically insulated from a continuous body region, a drift region separated from the at least two source regions by the body region, and at least three contact plugs extending from the body region towards a source electrode in the vertical direction. The at least three contact plugs are arranged successively between the first and second gate electrodes. Only the two outermost contact plugs that are arranged closest to the first and second gate electrodes, respectively, directly adjoin at least one of the source regions.Type: ApplicationFiled: June 4, 2020Publication date: December 10, 2020Inventors: Franz Hirler, Christian Fachmann, Winfried Kaindl, Hans Weber
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Publication number: 20200312998Abstract: A transistor device includes transistor cells each having source and drift regions of a first doping type and a body region of a second doping type in a first region of a semiconductor body, and a gate electrode dielectrically insulated from the body region. A gate conductor arranged on top of a second region of the semiconductor body is electrically connected to each gate electrode. A source conductor arranged on top of the first region is connected to each source and body region. A discharging region of the second doping type is arranged in the second region and located at least partially below the gate conductor, and includes at least one lower dose section in which a doping dose is lower than a minimum doping dose in other sections of the discharging region. The at least one lower dose section is associated with a corner of the gate conductor.Type: ApplicationFiled: March 19, 2020Publication date: October 1, 2020Inventors: Winfried Kaindl, Gabor Mezoesi, Enrique Vecino Vazquez
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Publication number: 20200105918Abstract: A method and a transistor device are disclosed. The method includes: forming a trench in a first surface in an edge region of a semiconductor body; forming an insulation layer in the trench and on the first surface of the semiconductor body; and planarizing the insulation layer so that a trench insulation layer that fills the trench remains, wherein forming the insulation layer comprises a thermal oxidation process.Type: ApplicationFiled: September 30, 2019Publication date: April 2, 2020Inventors: Hans Weber, Christian Fachmann, Franz Hirler, Winfried Kaindl, Markus Rochel
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Publication number: 20190319110Abstract: A transistor device includes at least one transistor cell, having, in a semiconductor body, a source region of a first doping type in a body region of a second doping type, a drain region, and a drift region of the first doping type adjoining the body region and arranged between the body region and the drain region. A low-resistance region of the second doping type in the body region adjoins the source region. A gate electrode dielectrically insulated from the source and body regions by a gate dielectric is arranged above a first surface of the semiconductor body. A length of an overlap between the source region and the gate electrode is larger than 70 nanometers. A doping profile of the low-resistance region along a line that is vertical to the first surface and goes through an edge of the gate electrode has a maximum of higher than 1E19 cm?3.Type: ApplicationFiled: June 25, 2019Publication date: October 17, 2019Inventors: Katarzyna Kowalik-Seidl, Bjoern Fischer, Winfried Kaindl, Markus Schmitt, Matthias Wegscheider
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Patent number: 10374056Abstract: Disclosed is a method for producing a transistor device and a transistor device. The method includes: forming a source region of a first doping type in a body region of a second doping type in a semiconductor body; and forming a low-resistance region of the second doping type adjoining the source region in the body region. Forming the source region includes implanting dopant particles of the first doping type using an implantation mask via a first surface of the semiconductor body into the body region. Implanting the doping particles of the first doping type includes a tilted implantation.Type: GrantFiled: October 28, 2016Date of Patent: August 6, 2019Assignee: Infineon Technologies Austria AGInventors: Katarzyna Kowalik-Seidl, Bjoern Fischer, Winfried Kaindl, Markus Schmitt, Matthias Wegscheider
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Patent number: 10256325Abstract: According to an embodiment, a method of forming a power semiconductor device is provided. The method includes providing a semiconductor substrate and forming an epitaxial layer on the semiconductor substrate. The epitaxial layer includes a body region, a source region, and a drift region. The method further includes forming a dielectric layer on the epitaxial layer. The dielectric layer is formed thicker above a drift region of the epitaxial layer than above at least part of the body region and the dielectric layer is formed at a temperature less than 950° C.Type: GrantFiled: November 8, 2012Date of Patent: April 9, 2019Assignee: Infineon Technologies Austria AGInventors: Stefan Gamerith, Markus Schmitt, Winfried Kaindl, Gerald Sölkner
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Patent number: 9899510Abstract: The present disclosure provides a semiconductor device, which includes a compensation area which includes p-regions and n-regions, and a plurality of transistor cells on the compensation area. Each of the plurality of transistor cells includes a source region, a body region, a gate and an interlayer dielectric, and a source metallization layer arranged on the interlayer dielectric. The semiconductor device further includes an additional n-doping region that is provided on top of the n-regions between two neighboring body regions, and a source plug which fills a contact hole formed through the interlayer dielectric between the source and body region and the source metallization layer, so as to electrically connect the source and body region and the source metallization layer.Type: GrantFiled: November 11, 2016Date of Patent: February 20, 2018Assignee: Infineon Technologies Austria AGInventors: Winfried Kaindl, Franz Hirler, Armin Willmeroth
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Patent number: 9722020Abstract: A super junction semiconductor device includes a semiconductor portion with first and second surfaces parallel to one another and including a doped layer of a first conductivity type formed at least in a cell area. Columnar first super junction regions of a second conductivity type extend in a direction perpendicular to the first surface and are separated by columnar second super junction regions of the first conductivity type. The first and second super junction regions form a super junction structure between the first surface and the doped layer. A first electrode structure directly adjoins the first surface and a second electrode structure directly adjoins the second surface. The first electrode structure has a first thickness and the second electrode structure has a second thickness. A sum of the first and second thicknesses is at least 20% of the thickness of the semiconductor portion between the first and second surfaces.Type: GrantFiled: May 20, 2016Date of Patent: August 1, 2017Assignee: Infineon Technologies Austria AGInventors: Armin Willmeroth, Franz Hirler, Hans-Joachim Schulze, Uwe Wahl, Winfried Kaindl
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Publication number: 20170125580Abstract: Disclosed is a method for producing a transistor device and a transistor device. The method includes: forming a source region of a first doping type in a body region of a second doping type in a semiconductor body; and forming a low-resistance region of the second doping type adjoining the source region in the body region. Forming the source region includes implanting dopant particles of the first doping type using an implantation mask via a first surface of the semiconductor body into the body region. Implanting the doping particles of the first doping type includes a tilted implantation.Type: ApplicationFiled: October 28, 2016Publication date: May 4, 2017Inventors: Katarzyna Kowalik-Seidl, Bjoern Fischer, Winfried Kaindl, Markus Schmitt, Matthias Wegscheider
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Publication number: 20170062605Abstract: The present disclosure provides a semiconductor device, which includes a compensation area which includes p-regions and n-regions, and a plurality of transistor cells on the compensation area. Each of the plurality of transistor cells includes a source region, a body region, a gate and an interlayer dielectric, and a source metallization layer arranged on the interlayer dielectric. The semiconductor device further includes an additional n-doping region that is provided on top of the n-regions between two neighboring body regions, and a source plug which fills a contact hole formed through the interlayer dielectric between the source and body region and the source metallization layer, so as to electrically connect the source and body region and the source metallization layer.Type: ApplicationFiled: November 11, 2016Publication date: March 2, 2017Inventors: Winfried Kaindl, Franz Hirler, Armin Willmeroth
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Patent number: 9524966Abstract: The present disclosure provides a semiconductor device, which includes a compensation area which includes p-regions and n-regions, and a plurality of transistor cells on the compensation area. Each of the plurality of transistor cells includes a source region, a body region, a gate and an interlayer dielectric, and a source metallization layer arranged on the interlayer dielectric. The semiconductor device further includes an additional n-doping region that is provided on top of the n-regions between two neighboring body regions, and a source plug which fills a contact hole formed through the interlayer dielectric between the source and body region and the source metallization layer, so as to electrically connect the source and body region and the source metallization layer.Type: GrantFiled: October 30, 2014Date of Patent: December 20, 2016Assignee: Infineon Technologies Austria AGInventors: Winfried Kaindl, Franz Hirler, Armin Willmeroth
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Publication number: 20160268370Abstract: A super junction semiconductor device includes a semiconductor portion with first and second surfaces parallel to one another and including a doped layer of a first conductivity type formed at least in a cell area. Columnar first super junction regions of a second conductivity type extend in a direction perpendicular to the first surface and are separated by columnar second super junction regions of the first conductivity type. The first and second super junction regions form a super junction structure between the first surface and the doped layer. A first electrode structure directly adjoins the first surface and a second electrode structure directly adjoins the second surface. The first electrode structure has a first thickness and the second electrode structure has a second thickness. A sum of the first and second thicknesses is at least 20% of the thickness of the semiconductor portion between the first and second surfaces.Type: ApplicationFiled: May 20, 2016Publication date: September 15, 2016Inventors: Armin Willmeroth, Franz Hirler, Hans-Joachim Schulze, Uwe Wahl, Winfried Kaindl
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Patent number: 9349792Abstract: A super junction semiconductor device includes a semiconductor portion with a first surface and a second surface parallel to the first surface. The semiconductor portion includes a doped layer of a first conductivity type formed at least in a cell area. The super junction semiconductor device further includes columnar first super junction regions of a second, opposite conductivity type extending in a direction perpendicular to the first surface and separated by columnar second super junction regions of the first conductivity type. The first and second super junction regions form a super junction structure between the first surface and the doped layer. A distance between the first super junction regions and the second surface does not exceed 30 ?m.Type: GrantFiled: January 29, 2015Date of Patent: May 24, 2016Assignee: Infineon Technologies Austria AGInventors: Armin Willmeroth, Franz Hirler, Hans-Joachim Schulze, Uwe Wahl, Winfried Kaindl