Patents by Inventor Wing Yu

Wing Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11967556
    Abstract: Methods for forming microelectronic devices include forming a staircase structure in a stack structure having a vertically alternating sequence of insulative and conductive materials arranged in tiers. Steps are at lateral ends of the tiers. Contact openings of different aspect ratios are formed in fill material adjacent the staircase structure, with some openings terminating in the fill material and others exposing portions of the conductive material of upper tiers of the stack structure. Additional conductive material is selectively formed on the exposed portions of the conductive material. The contact openings initially terminating in the fill material are extended to expose portions of the conductive material of lower elevations. Contacts are formed, with some extending to the additional conductive material and others extending to conductive material of the tiers of the lower elevations. Microelectronic devices and systems incorporating such staircase structures and contacts are also disclosed.
    Type: Grant
    Filed: October 25, 2021
    Date of Patent: April 23, 2024
    Inventors: Biow Hiem Ong, David A. Daycock, Chieh Hsien Quek, Chii Wean Calvin Chen, Christian George Emor, Wing Yu Lo
  • Publication number: 20240117362
    Abstract: Embodiments of the present disclosure relate to lipid-PEGylated solid support and phosphoramidites derivatives, methods for preparing the same, and their uses in the delivery of oligonucleotide drugs to the cellular targets.
    Type: Application
    Filed: August 16, 2023
    Publication date: April 11, 2024
    Inventors: Mufa Zou, David Yu, Aldrich N.K. Lau, Ruiming Zou, Wing C. Poon, Gang Zhao, Gengyu Du, Yun-Chiao Yao, Allen Wong, Xiaojun Li
  • Publication number: 20240101609
    Abstract: Embodiments of a recombinant human Parainfluenza Virus (hPIV) F ectodomain trimer stabilized in a prefusion conformation are provided. Also disclosed are nucleic acids encoding the hPIV F ectodomain trimer and methods of producing the hPIV F ectodomain trimer. Methods for inducing an immune response in a subject are also disclosed. In some embodiments, the method can be a method for treating or inhibiting a hPIV infection in a subject by administering a effective amount of the recombinant hPIV F ectodomain trimer to the subject.
    Type: Application
    Filed: December 12, 2023
    Publication date: March 28, 2024
    Applicants: The United States of America, as represented by the Secretary, Department of Health and Human Servi, Institute for Research in Biomedicine
    Inventors: Baoshan Zhang, Guillaume Stewart-Jones, Tongqing Zhou, John Mascola, Kai Xu, Yongping Yang, Paul Thomas, Gwo-Yu Chuang, Li Ou, Peter Kwong, Yaroslav Tsybovsky, Wing-Pui Kong, Aliaksandr Druz, Davide Corti, Antonio Lanzavecchia
  • Patent number: 11935115
    Abstract: System and methods for management of third party satellite radio activation/deactivation by a vehicle rental service company, wherein satellite radio services may be provided in a rental car when requested by a customer. The systems and methods will enable activation of a satellite radio shortly before or at the start of the rental period, and activation may be altered by the vehicle rental service company in the event that the rental period is shortened or extended, or if the vehicle is exchanged. The systems and methods deactivate the satellite radio service at the end of the rental period. The systems and methods may also be used to activate or deactivate other equipment or services made available via a vehicle rental service company in response to a customer request.
    Type: Grant
    Filed: December 21, 2021
    Date of Patent: March 19, 2024
    Assignee: AVIS BUDGET CAR RENTAL, LLC
    Inventors: Wing Yu Joseph Chan, Michael J. Caron
  • Patent number: 11798845
    Abstract: Method for forming tungsten gap fill on a structure, including high aspect ratio structures includes depositing a tungsten liner in the structure using a physical vapor deposition (PVD) process with high ionization and an ambient gas of argon or krypton. The PVD process is performed at a temperature of approximately 20 degrees Celsius to approximately 300 degrees Celsius. The method further includes treating the structure with a nitridation process and depositing bulk fill tungsten into the structure using a chemical vapor deposition (CVD) process to form a seam suppressed boron free tungsten fill. The CVD process is performed at a temperature of approximately 300 degrees Celsius to approximately 500 degrees Celsius and at a pressure of approximately 5 Torr to approximately 300 Torr.
    Type: Grant
    Filed: October 28, 2020
    Date of Patent: October 24, 2023
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Xi Cen, Kai Wu, Min Heon, Wei Min Chan, Tom Ho Wing Yu, Peiqi Wang, Ju Ik Kang, Feihu Wang, Nobuyuki Sasaki, Chunming Zhou
  • Patent number: 11637107
    Abstract: Bit line stacks and methods of forming bit line stacks are described herein. A bit line stack comprises: a polysilicon layer; an adhesion layer on the polysilicon layer; a barrier metal layer on the adhesion layer; an interface layer on the barrier metal layer; a resistance reducing layer on the interface layer; and a conductive layer on the resistance reducing layer. A bit line stack having the resistance reducing layer has a resistance at least 5% lower than a comparable bit line stack without the resistance reducing layer. The resistance reducing layer may include silicon oxide or silicon nitride. The resistance reducing layer may be formed using one or more of a physical vapor deposition (PVD), a radio frequency-PVD, a pulsed-PVD, chemical vapor deposition (CVD), atomic layer deposition (ALD) or sputtering process.
    Type: Grant
    Filed: June 17, 2021
    Date of Patent: April 25, 2023
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Tom Ho Wing Yu, Nobuyuki Sasaki, Jianxin Lei, Wenting Hou, Rongjun Wang, Tza-Jing Gung
  • Publication number: 20230115130
    Abstract: Embodiments of the present disclosure generally relate to methods for forming or otherwise producing metal silicides on a silicon surface of substrate. Exemplary metal silicides can be or include titanium silicide, cobalt silicide, nickel silicide, molybdenum silicide, or alloys thereof. In one or more embodiments, a method of forming a metal silicide is provided and includes removing a native oxide from a substrate to reveal a silicon surface of the substrate during a cleaning process, depositing a metallic layer on the silicon surface during a deposition process, and heating the substrate contained within a process region containing hydrogen gas during a silicidation process to produce a metal silicide layer on the substrate from the metallic layer and the silicon surface.
    Type: Application
    Filed: October 13, 2021
    Publication date: April 13, 2023
    Inventors: Tom Ho Wing YU, Nobuyuki SASAKI
  • Patent number: 11626410
    Abstract: Bit line stacks and methods of forming bit line stacks are described herein. A bit line stack comprises: a polysilicon layer; an adhesion layer on the polysilicon layer; a barrier metal layer on the adhesion layer; an interface layer on the barrier metal layer; a resistance reducing layer on the interface layer; and a conductive layer on the resistance reducing layer. A bit line stack having the resistance reducing layer has a resistance at least 5% lower than a comparable bit line stack without the resistance reducing layer. The resistance reducing layer may include silicon oxide or silicon nitride. The resistance reducing layer may be formed using one or more of a physical vapor deposition (PVD), a radio frequency-PVD, a pulsed-PVD, chemical vapor deposition (CVD), atomic layer deposition (ALD) or sputtering process.
    Type: Grant
    Filed: July 11, 2022
    Date of Patent: April 11, 2023
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Tom Ho Wing Yu, Nobuyuki Sasaki, Jianxin Lei, Wenting Hou, Rongjun Wang, Tza-Jing Gung
  • Patent number: 11607403
    Abstract: The therapeutic uses of febuxostat or febuxostat derivatives and compositions comprising febuxostat or febuxostat derivatives to promote neurogenesis for the treatment of disease.
    Type: Grant
    Filed: November 8, 2016
    Date of Patent: March 21, 2023
    Assignee: Morningside Ventures Limited
    Inventors: Nancy Yuk-Yu Ip, Wing-Yu Fu, Fanny Chui Fun Ip, Kit Yu Fu
  • Publication number: 20220406788
    Abstract: Bit line stacks and methods of forming bit line stacks are described herein. A bit line stack comprises: a polysilicon layer; an adhesion layer on the polysilicon layer; a barrier metal layer on the adhesion layer; an interface layer on the barrier metal layer; a resistance reducing layer on the interface layer; and a conductive layer on the resistance reducing layer. A bit line stack having the resistance reducing layer has a resistance at least 5% lower than a comparable bit line stack without the resistance reducing layer. The resistance reducing layer may include silicon oxide or silicon nitride. The resistance reducing layer may be formed using one or more of a physical vapor deposition (PVD), a radio frequency-PVD, a pulsed-PVD, chemical vapor deposition (CVD), atomic layer deposition (ALD) or sputtering process.
    Type: Application
    Filed: June 17, 2021
    Publication date: December 22, 2022
    Applicant: Applied Materials, Inc.
    Inventors: Tom Ho Wing Yu, Nobuyuki Sasaki, Jianxin Lei, Wenting Hou, Rongjun Wang, Tza-Jing Gung
  • Publication number: 20220406790
    Abstract: Bit line stacks and methods of forming bit line stacks are described herein. A bit line stack comprises: a polysilicon layer; an adhesion layer on the polysilicon layer; a barrier metal layer on the adhesion layer; an interface layer on the barrier metal layer; a resistance reducing layer on the interface layer; and a conductive layer on the resistance reducing layer. A bit line stack having the resistance reducing layer has a resistance at least 5% lower than a comparable bit line stack without the resistance reducing layer. The resistance reducing layer may include silicon oxide or silicon nitride. The resistance reducing layer may be formed using one or more of a physical vapor deposition (PVD), a radio frequency-PVD, a pulsed-PVD, chemical vapor deposition (CVD), atomic layer deposition (ALD) or sputtering process.
    Type: Application
    Filed: July 11, 2022
    Publication date: December 22, 2022
    Applicant: Applied Materials, Inc.
    Inventors: Tom Ho Wing Yu, Nobuyuki Sasaki, Jianxin Lei, Wenting Hou, Rongjun Wang, Tza-Jing Gung
  • Publication number: 20220336274
    Abstract: Method for forming tungsten gap fill on a structure, including high aspect ratio structures includes depositing a tungsten liner in the structure using a physical vapor deposition (PVD) process with high ionization and an ambient gas of argon or krypton. The PVD process is performed at a temperature of approximately 20 degrees Celsius to approximately 300 degrees Celsius. The method further includes treating the structure with a nitridation process and depositing bulk fill tungsten into the structure using a chemical vapor deposition (CVD) process to form a seam suppressed boron free tungsten fill. The CVD process is performed at a temperature of approximately 300 degrees Celsius to approximately 500 degrees Celsius and at a pressure of approximately 5 Torr to approximately 300 Torr.
    Type: Application
    Filed: July 5, 2022
    Publication date: October 20, 2022
    Inventors: Xi CEN, Kai WU, Min HEON, Wei Min CHAN, Tom Ho Wing YU, Peiqi WANG, Ju Ik KANG, Feihu WANG, Nobuyuki SASAKI, Chunming ZHOU
  • Publication number: 20220130724
    Abstract: Method for forming tungsten gap fill on a structure, including high aspect ratio structures includes depositing a tungsten liner in the structure using a physical vapor deposition (PVD) process with high ionization and an ambient gas of argon or krypton. The PVD process is performed at a temperature of approximately 20 degrees Celsius to approximately 300 degrees Celsius. The method further includes treating the structure with a nitridation process and depositing bulk fill tungsten into the structure using a chemical vapor deposition (CVD) process to form a seam suppressed boron free tungsten fill. The CVD process is performed at a temperature of approximately 300 degrees Celsius to approximately 500 degrees Celsius and at a pressure of approximately 5 Torr to approximately 300 Torr.
    Type: Application
    Filed: October 28, 2020
    Publication date: April 28, 2022
    Inventors: Xi CEN, Kai WU, Min HEON, Wei Min CHAN, Tom Ho Wing YU, Peiqi WANG, Ju Ik KANG, Feihu WANG, Nobuyuki SASAKI, Chunming ZHOU
  • Publication number: 20220045007
    Abstract: Methods for forming microelectronic devices include forming a staircase structure in a stack structure having a vertically alternating sequence of insulative and conductive materials arranged in tiers. Steps are at lateral ends of the tiers. Contact openings of different aspect ratios are formed in fill material adjacent the staircase structure, with some openings terminating in the fill material and others exposing portions of the conductive material of upper tiers of the stack structure. Additional conductive material is selectively formed on the exposed portions of the conductive material. The contact openings initially terminating in the fill material are extended to expose portions of the conductive material of lower elevations. Contacts are formed, with some extending to the additional conductive material and others extending to conductive material of the tiers of the lower elevations. Microelectronic devices and systems incorporating such staircase structures and contacts are also disclosed.
    Type: Application
    Filed: October 25, 2021
    Publication date: February 10, 2022
    Inventors: Biow Hiem Ong, David A. Daycock, Chieh Hsien Quek, Chii Wean Calvin Chen, Christian George Emor, Wing Yu Lo
  • Patent number: 11205221
    Abstract: System and methods for management of third party satellite radio activation/deactivation by a vehicle rental service company, wherein satellite radio services may be provided in a rental car when requested by a customer. The systems and methods will enable activation of a satellite radio shortly before or at the start of the rental period, and activation may be altered by the vehicle rental service company in the event that the rental period is shortened or extended, or if the vehicle is exchanged. The systems and methods deactivate the satellite radio service at the end of the rental period. The systems and methods may also be used to activate or deactivate other equipment or services made available via a vehicle rental service company in response to a customer request.
    Type: Grant
    Filed: March 17, 2020
    Date of Patent: December 21, 2021
    Assignee: AVIS BUDGET CAR RENTAL, LLC
    Inventors: Wing Yu Joseph Chan, Michael J. Caron
  • Patent number: 11158577
    Abstract: Methods for forming microelectronic devices include forming a staircase structure in a stack structure having a vertically alternating sequence of insulative and conductive materials arranged in tiers. Steps are at lateral ends of the tiers. Contact openings of different aspect ratios are formed in fill material adjacent the staircase structure, with some openings terminating in the fill material and others exposing portions of the conductive material of upper tiers of the stack structure. Additional conductive material is selectively formed on the exposed portions of the conductive material. The contact openings initially terminating in the fill material are extended to expose portions of the conductive material of lower elevations. Contacts are formed, with some extending to the additional conductive material and others extending to conductive material of the tiers of the lower elevations. Microelectronic devices and systems incorporating such staircase structures and contacts are also disclosed.
    Type: Grant
    Filed: January 31, 2020
    Date of Patent: October 26, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Biow Hiem Ong, David A. Daycock, Chieh Hsien Quek, Chii Wean Calvin Chen, Christian George Emor, Wing Yu Lo
  • Publication number: 20210327717
    Abstract: Methods and apparatus for the formation of cobalt disilicide are described. Some embodiments of the disclosure provide in-situ methods of forming cobalt disilicide. The resulting films are smoother and have lower resistance and resistivity than films formed by similar ex-situ methods. Some embodiments of the disclosure provide apparatus for performing the described methods without an air break between processes.
    Type: Application
    Filed: April 15, 2020
    Publication date: October 21, 2021
    Applicant: Applied Materials, Inc.
    Inventors: Tom Ho Wing Yu, Nobuyuki Sasaki, Kazuya Daito
  • Publication number: 20210242131
    Abstract: Methods for forming microelectronic devices include forming a staircase structure in a stack structure having a vertically alternating sequence of insulative and conductive materials arranged in tiers. Steps are at lateral ends of the tiers. Contact openings of different aspect ratios are formed in fill material adjacent the staircase structure, with some openings terminating in the fill material and others exposing portions of the conductive material of upper tiers of the stack structure. Additional conductive material is selectively formed on the exposed portions of the conductive material. The contact openings initially terminating in the fill material are extended to expose portions of the conductive material of lower elevations. Contacts are formed, with some extending to the additional conductive material and others extending to conductive material of the tiers of the lower elevations. Microelectronic devices and systems incorporating such staircase structures and contacts are also disclosed.
    Type: Application
    Filed: January 31, 2020
    Publication date: August 5, 2021
    Inventors: Biow Hiem Ong, David A. Daycock, Chieh Hsien Quek, Chii Wean Calvin Chen, Christian George Emor, Wing Yu Lo
  • Publication number: 20210171645
    Abstract: The present invention provides new, fully human EphA4 monoclonal antibodies with distinct binding characteristics. Also disclosed are antigen binding fragments of these antibodies, bispecific forms of these antibodies, and conjugates of these antibodies. In addition, nucleic acids encoding these antibodies, antigen binding fragments, bispecific antibodies and conjugates are disclosed. These monoclonal antibodies, antigen binding fragments, bispecific antibodies, conjugates, nucleic acids and vectors are of use for identifying and treating a subject with a disease or condition involving abnormal EphA4-mediated signaling.
    Type: Application
    Filed: February 15, 2021
    Publication date: June 10, 2021
    Inventors: Nancy Yuk-Yu Ip, Kit Yu Fu, Wing Yu Fu, Dimiter S. Dimitrov, Tianlei Ying
  • Patent number: D1023269
    Type: Grant
    Filed: November 23, 2021
    Date of Patent: April 16, 2024
    Assignee: PURACLENZ LLC
    Inventors: Christopher Patrick Dooley, Wing Kau Spencer Fok, Tin Yu Wong