Abstract: An oil and gas collection system, comprising a source of oil and gas flowing into a body of water; a collector located adjacent the source of oil and gas; a riser to transport the oil and gas towards a surface of the body of water, a first end of the riser fluidly connected to the collector; and a separator fluidly connected to a second end of the riser, the separator adapted to separate the oil and gas into a first oil rich stream and a second gas rich stream, the separator comprising an oil rich stream outlet and a gas rich stream outlet. In some embodiments, the source of oil and gas comprises a blow out preventer.

Abstract: Some embodiments of the invention provide components and/or techniques that may assist in choosing a snapshot to which to roll back to address a system malfunction. For example, some embodiments of the invention may record various metrics describing the system's performance, reliability and/or functionality at the points at which various snapshots are taken, along any of numerous dimensions. When a user later indicates a desire to restore the system to a previous point, these metrics may be analyzed to choose a snapshot to which to roll back.

Abstract: There is disclosed a system comprising a well drilled into an underground formation comprising hydrocarbons; a production facility at a topside of the well; a water production facility connected to the production facility; wherein the water production facility produces water by removing some multivalent ions, then removing some monovalent ions, and then adding back some monovalent ions, and then injects the water into the well.

Abstract: There is disclosed a system comprising a well drilled into an underground formation comprising hydrocarbons; a production facility at a topside of the well; a water production facility connected to the production facility; wherein the water production facility produces water by removing some multivalent ions, then removing some monovalent ions, and then adding back some multivalent ions, and then injects the water into the well.

Abstract: One embodiment of the present invention provides a system for efficiently evaluating a security policy. During operation, the system retrieves one or more roles associated with the user. Next, the system checks if a session-level cache exists for a set of Access Control Entries (ACEs) which is associated with the one or more roles. If this session-level cache exists, the system returns the set of ACEs from the session-level cache. Otherwise, the system generates the set of ACEs associated with the one or more roles from an Access Control List (ACL). During operation, the system can also update the one or more roles associated with the user and update the set of ACEs based on the updated one or more roles and the ACL. The system subsequently updates the session level cache with the updated set of ACEs and updated one or more roles.

Abstract: A processor-based system may include a main processor and a coprocessor. The coprocessor handles instructions that include opcodes specifying a data processing operation to be performed by the coprocessor and a coprocessor identification field for identifying a target coprocessor for coprocessor instructions. Two bits indicate one of four data sizes including a byte (8 bits), a half word (16 bits), a word (32 bits), and a double word (64 bits). Two other bits indicate a saturation type.

Abstract: A method and system for providing global self-service transaction terminals or automatic teller machines (ATMs) affords worldwide web content to ATM customers, centralized management for ATM operators, and supports local and remote administration for ATM field service personnel. The system includes multiple ATMs coupled over a network to a host, and the ATMs are provided with a touch screen interface and an interface for visually impaired persons. The ATMs enable both local and remote administration of ATM operations by bank personnel and an integrated network control. The ATMs are web-enabled, and ATM communications are performed over a communications network.

Abstract: A fault-tolerant, high-speed wafer scale system comprises a plurality of functional modules, a parallel hierarchical bus which is fault-tolerant to defects in an interconnect network, and one or more bus masters. This bus includes a plurality of bus lines segmented into sections and linked together by programmable bus switches and bus transceivers or repeaters in an interconnect network.

Abstract: A memory system includes a plurality of memory modules, each including at least one memory array. Each memory array has an associated line of sense amplifier latches, wherein each line of sense amplifier latches is activated independently. Each line of sense amplifier latches is capable of caching a row of data from the associated memory array. The capacity of each memory array and the number of memory arrays are selected such that a cache hit rate of over 90 percent is achieved for the memory system.

Abstract: A fault-tolerant, high-speed wafer scale system comprises a plurality of functional modules, a parallel hierarchical bus which is fault-tolerant to defects in an interconnect network, and one or more bus masters. This bus includes a plurality of bus lines segmented into sections and linked together by programmable bus switches and bus transceivers or repeaters in an interconnect network.

Abstract: A fault-tolerant, high-speed wafer scale system comprises a plurality of functional modules, a parallel hierarchical bus which is fault-tolerant to defects in an interconnect network, and one or more bus masters. This bus includes a plurality of bus lines segmented into sections and linked together by programmable bus switches and bus transceivers or repeaters in an interconnect network.

Abstract: A fault-tolerant, high-speed wafer scale system includes a plurality of functional memory modules, each having associated sense amplifiers which act as high-speed cache memory, a parallel hierarchical bus which is fault-tolerant to defects and a interconnect network, and one or more bus masters. By grouping the DRAM arrays into logically independent modules of relatively small memory capacity (588 Kbit), a large number of cache lines (128) is obtained at small main memory capacity (4 Megabytes). The large number of cache lines allows maintaining a high cache hit rate (greater than 90%).

Abstract: A fault-tolerant, high-speed wafer scale system comprises a plurality of functional modules, a parallel hierarchical bus which is fault-tolerant to defects in an interconnect network, and one or more bus masters. This bus includes a plurality of bus lines segmented into sections and linked together by programmable bus switches and bus transceivers or repeaters in an interconnect network.

Abstract: Geophones are placed around pipelines to detect third parties, e.g., heavy construction vehicles. Associated computer equipment acquires data from the geophones and discriminates for the frequencies associated with heavy construction vehicles.