Patents by Inventor Wingyu Leung

Wingyu Leung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9767914
    Abstract: A method of a state machine executing instructions related to program-erase operations performed on a non-volatile memory is disclosed. The method includes implementing a program-erase loop counter in the state machine, and presetting a threshold for an electric current of memory cells and a step time for each of the program and the erase operation. Based on repeatedly executing a number of comparison and verification operations, each for a duration of the preset step time until the program-erase loop counter reaches a maximum value thereof, the electric current of the each programmed-erased memory cell is maintained at a desired level thereof following termination of the each of the program and the erase operation.
    Type: Grant
    Filed: October 10, 2016
    Date of Patent: September 19, 2017
    Inventor: Wingyu Leung
  • Patent number: 8489843
    Abstract: A method includes forming a memory device through providing an array of non-volatile memory cells including one or more non-volatile memory cell(s) and an array of volatile memory cells including one or more volatile memory cell(s) on a substrate. The method also includes appropriately programming an address translation logic associated with the memory device through a set of registers associated therewith to enable configurable mapping of an address associated with a sector of the memory device to any memory address space location in a computing system associated with the memory device. The address translation logic is configured to enable translation of an external virtual address associated with the sector of the memory device to a physical address associated therewith.
    Type: Grant
    Filed: April 20, 2010
    Date of Patent: July 16, 2013
    Assignee: Chip Memory Technology, Inc.
    Inventor: Wingyu Leung
  • Patent number: 8391078
    Abstract: A non-volatile DRAM cell includes a pass-gate transistor and a cell capacitor. A read operation of the non-volatile cell begins by positively charging the cell capacitor. A cell capacitor of an associated dummy non-volatile DRAM cell is fully charged. The pass-gate transistor is activated and if the pass-gate transistor is erased it does not turn on and if it is programmed, it turns on. Charge is shared on the complementary pair of pre-charged bit lines connected to the non-volatile DRAM cell and its associated Dummy non-volatile DRAM cell. A sense amplifier detects the difference in the data state stored in the pass-gate transistor. The program and erase of the non-volatile DRAM cell is accomplished Gate-induced drain-lowering (GIDL) assisted band-to-band tunneling and Fowler-Nordheim tunneling respectively. Programming or erasing a selected row of cells does not affect the data states of the cells in the unselected rows.
    Type: Grant
    Filed: May 25, 2010
    Date of Patent: March 5, 2013
    Assignee: Chip Memory Technology, Inc.
    Inventor: Wingyu Leung
  • Patent number: 8228726
    Abstract: A system and method of an electrically programmable and erasable non-volatile memory cell fabricated using a single-poly, logic process with the addition of ONO deposition and etching is disclosed. In one embodiment, a non-volatile memory system includes at least one non-volatile memory cell consists of a SONOS transistor fabricated on a P substrate, with a deep N-well located in the P substrate, with a P-well located in the deep N-well. The memory cell further includes an access NMOS transistor, coupled to the SONOS transistor and located in the same P-well that includes an oxide only gate-dielectric. The cell can be fabricated in a modified logic process with other transistors and with their physical characteristics preserved.
    Type: Grant
    Filed: October 18, 2010
    Date of Patent: July 24, 2012
    Assignee: Chip Memory Technology, Inc.
    Inventors: Gang-Feng Fang, Wingyu Leung
  • Publication number: 20110258364
    Abstract: A method includes forming a memory device through providing an array of non-volatile memory cells including one or more non-volatile memory cell(s) and an array of volatile memory cells including one or more volatile memory cell(s) on a substrate. The method also includes appropriately programming an address translation logic associated with the memory device through a set of registers associated therewith to enable configurable mapping of an address associated with a sector of the memory device to any memory address space location in a computing system associated with the memory device. The address translation logic is configured to enable translation of an external virtual address associated with the sector of the memory device to a physical address associated therewith.
    Type: Application
    Filed: April 20, 2010
    Publication date: October 20, 2011
    Applicant: CHIP MEMORY TECHNOLOGY, INC.,
    Inventor: Wingyu Leung
  • Patent number: 7983081
    Abstract: An apparatus and method of an electrically programmable and erasable non-volatile memory cell with a deep N-well to isolate the memory cell from the substrate is disclosed. In one embodiment, a non-volatile memory apparatus includes at least one non-volatile memory cell fabricated on a P substrate, with a deep N-well located in the P substrate, while a P-well and an N-well are located in the deep N-well. The memory cell further includes a PMOS transistor located in the N-well, in which the PMOS transistor includes a PMOS gate-oxide, and an NMOS capacitor located in the P-well. The NMOS capacitor includes an N+ coupling region located in the P-well, and an NMOS gate-oxide. The memory cell further includes a floating gate comprised of a poly-silicon gate overlying the PMOS transistor and the NMOS capacitor.
    Type: Grant
    Filed: December 14, 2008
    Date of Patent: July 19, 2011
    Assignee: Chip.Memory Technology, Inc.
    Inventors: Gang-Feng Fang, Wingyu Leung
  • Patent number: 7919367
    Abstract: A non-volatile memory cell with increased charge retention is fabricated on the same substrate as logic devices using a single-gate conventional logic process. A silicide-blocking dielectric structure is formed over a floating gate of the NVM cell, thereby preventing silicide formation over the floating gate, while allowing silicide formation over the logic devices. Silicide spiking and bridging are prevented in the NVM cell, as silicide-blocking dielectric structure prevents silicide metal from coming in contact with the floating gate or adjacent sidewall spacers. The silicide-blocking dielectric layer may expose portions of the active regions of the NVM cell, away from the floating gate and adjacent sidewall spacers, thereby enabling silicide formation on these portions. Alternately, the silicide-blocking dielectric layer may cover the active regions of the NVM cell during silicide formation. In this case, silicide-blocking dielectric layer may be thinned or removed after silicide formation.
    Type: Grant
    Filed: January 28, 2008
    Date of Patent: April 5, 2011
    Assignee: MoSys, Inc.
    Inventors: Gang-feng Fang, Dennis Sinitsky, Wingyu Leung
  • Publication number: 20110032766
    Abstract: A system and method of an electrically programmable and erasable non-volatile memory cell fabricated using a single-poly, logic process with the addition of ONO deposition and etching is disclosed. In one embodiment, a non-volatile memory system includes at least one non-volatile memory cell consists of a SONOS transistor fabricated on a P substrate, with a deep N-well located in the P substrate, with a P-well located in the deep N-well. The memory cell further includes an access NMOS transistor, coupled to the SONOS transistor and located in the same P-well that includes an oxide only gate-dielectric. The cell can be fabricated in a modified logic process with other transistors and with their physical characteristics preserved.
    Type: Application
    Filed: October 18, 2010
    Publication date: February 10, 2011
    Applicant: Chip Memory Technology, Inc.
    Inventors: GANG-FENG FANG, Wingyu Leung
  • Publication number: 20100238728
    Abstract: A non-volatile DRAM cell includes a pass-gate transistor and a cell capacitor. A read operation of the non-volatile cell begins by positively charging the cell capacitor. A cell capacitor of an associated dummy non-volatile DRAM cell is fully charged. The pass-gate transistor is activated and if the pass-gate transistor is erased it does not turn on and if it is programmed, it turns on. Charge is shared on the complementary pair of pre-charged bit lines connected to the non-volatile DRAM cell and its associated Dummy non-volatile DRAM cell. A sense amplifier detects the difference in to the data state stored in the pass-gate transistor. The program and erase of the non-volatile DRAM cell is accomplished Gate-induced drain-lowering (GIDL) assisted band-to-band tunneling and Fowler-Nordheim tunneling respectively. Programming or erasing a selected row of cells does not affect the data states of the cells in the unselected rows.
    Type: Application
    Filed: May 25, 2010
    Publication date: September 23, 2010
    Inventor: Wingyu Leung
  • Patent number: 7791975
    Abstract: A method and apparatus for scaling an embedded DRAM array from a first process to a second process, wherein the scaling involves reducing the linear dimensions of features by a constant scale factor. From the first process to the second process, DRAM cell capacitor layout area is reduced by the square of the scale factor, while cell capacitance is reduced by the scale factor. The voltage used to supply the logic transistors is scaled down from the first process to the second process. However, the voltage used to supply the sense amplifiers remains constant in both processes. Thus, in an embedded DRAM array of the second process, sense amplifiers are supplied by a greater voltage than the logic transistors. This allows the sensing voltage of DRAM cells to be maintained from one process generation to another, while allowing memory size to scale with the square of the process scale factor.
    Type: Grant
    Filed: March 13, 2008
    Date of Patent: September 7, 2010
    Assignee: MoSys, Inc.
    Inventor: Wingyu Leung
  • Publication number: 20100149874
    Abstract: An apparatus and method of an electrically programmable and erasable non-volatile memory cell with a deep N-well to isolate the memory cell from the substrate is disclosed. In one embodiment, a non-volatile memory apparatus includes at least one non-volatile memory cell fabricated on a P substrate, with a deep N-well located in the P substrate, while a P-well and an N-well are located in the deep N-well. The memory cell further includes a PMOS transistor located in the N-well, in which the PMOS transistor includes a PMOS gate-oxide, and an NMOS capacitor located in the P-well. The NMOS capacitor includes an N+ coupling region located in the P-well, and an NMOS gate-oxide. The memory cell further includes a floating gate comprised of a poly-silicon gate overlying the PMOS transistor and the NMOS capacitor.
    Type: Application
    Filed: December 14, 2008
    Publication date: June 17, 2010
    Inventors: WINGYU LEUNG, Gang-feng Fang
  • Patent number: 7684229
    Abstract: A method and apparatus for scaling an embedded DRAM array from a first process to a second process, wherein the scaling involves reducing the linear dimensions of features by a constant scale factor. From the first process to the second process, DRAM cell capacitor layout area is reduced by the square of the scale factor, while cell capacitance is reduced by the scale factor. The voltage used to supply the logic transistors is scaled down from the first process to the second process. However, the voltage used to supply the sense amplifiers remains constant in both processes. Thus, in an embedded DRAM array of the second process, sense amplifiers are supplied by a greater voltage than the logic transistors. This allows the sensing voltage of DRAM cells to be maintained from one process generation to another, while allowing memory size to scale with the square of the process scale factor.
    Type: Grant
    Filed: March 13, 2008
    Date of Patent: March 23, 2010
    Assignee: MoSys, Inc.
    Inventor: Wingyu Leung
  • Patent number: 7671401
    Abstract: A method, apparatus, and system in which an embedded memory fabricated in accordance with a conventional logic process includes one or more electrically-alterable non-volatile memory cells, each having a programming transistor, a read transistor and a control capacitor, which share a common floating gate electrode. The under-diffusion of the source/drain regions of the programming transistor and control capacitor are maximized. In one embodiment, the source/drain regions of the programming transistor are electrically shored by transistor punch-through (or direct contact).
    Type: Grant
    Filed: October 28, 2005
    Date of Patent: March 2, 2010
    Assignee: Mosys, Inc.
    Inventors: Gang-feng Fang, Dennis Sinitsky, Wingyu Leung
  • Patent number: 7633811
    Abstract: A non-volatile memory system including an array of cells, each having an access transistor and a capacitor sharing a floating gate. The access transistors in each row are fabricated in separate well regions, which are independently biased. Within each row, the source of each access transistor is coupled to a corresponding virtual ground line, and each capacitor structure is coupled to a corresponding word line. Alternately, the source of each access transistor in a column is coupled to a corresponding virtual ground line. Within each column, the drain of each access transistor is coupled to a corresponding bit line. Select memory cells in each row are programmed by band-to-band tunneling. Bit line biasing prevents programming of non-selected cells of the row. Programming is prevented in non-selected rows by controlling the well region voltages of these rows. Sector erase operations are implemented by Fowler-Nordheim tunneling.
    Type: Grant
    Filed: January 28, 2008
    Date of Patent: December 15, 2009
    Assignee: MoSys, Inc.
    Inventors: Gang-feng Fang, Wingyu Leung
  • Patent number: 7634707
    Abstract: A method for error detection and correction (EDC) includes: generating a complete EDC code in response to a data packet; distributing the complete EDC code among the data packet to create a plurality of bytes, each including a data portion from the data packet and an EDC code portion from the complete EDC code; storing the bytes in a memory module; retrieving the bytes from the memory module; forwarding the data portions of the bytes retrieved from the memory module to a requesting device; providing the data portions of the bytes retrieved from the memory module to an EDC functional block; providing the EDC code portions of the bytes retrieved from the memory module to the EDC functional block; and performing error checking and correction in the EDC functional block upon receiving the complete EDC code from the provided EDC code portions.
    Type: Grant
    Filed: March 11, 2004
    Date of Patent: December 15, 2009
    Assignee: MoSys, Inc.
    Inventors: Wingyu Leung, Fu-Chieh Hsu
  • Patent number: 7633810
    Abstract: A non-volatile memory system including an array of cells, each having an access transistor and a capacitor sharing a floating gate. The access transistors in each row are fabricated in separate well regions, which are independently biased. Within each row, the source of each access transistor is coupled to a corresponding virtual ground line, and each capacitor structure is coupled to a corresponding word line. Alternately, the source of each access transistor in a column is coupled to a corresponding virtual ground line. Within each column, the drain of each access transistor is coupled to a corresponding bit line. Select memory cells in each row are programmed by band-to-band tunneling. Bit line biasing prevents programming of non-selected cells of the row. Programming is prevented in non-selected rows by controlling the well region voltages of these rows. Sector erase operations are implemented by Fowler-Nordheim tunneling.
    Type: Grant
    Filed: January 28, 2008
    Date of Patent: December 15, 2009
    Assignee: MoSys, Inc.
    Inventors: Gang-feng Fang, Wingyu Leung
  • Patent number: 7533222
    Abstract: A dual-port memory system is implemented using single-port memory cells. An access arbiter having a synchronization circuit is used to prioritize and synchronize the access requests associated with the two ports. The access arbiter can also prioritize and synchronize refresh requests, in the case where the single-port memory cells require refresh. Access requests on the two ports and the refresh requests can be asynchronous. The access arbiter synchronizes the various requests by latching the requests into first-stage registers when a row access signal (RAS) is activated, and subsequently latching the contents of the first-stage registers into second-stage registers after a selected delay.
    Type: Grant
    Filed: June 29, 2006
    Date of Patent: May 12, 2009
    Assignee: MoSys, Inc.
    Inventor: Wingyu Leung
  • Patent number: 7522456
    Abstract: A non-volatile memory system including an array of cells, each having an access transistor and a capacitor sharing a floating gate. The access transistors in each row are fabricated in separate well regions, which are independently biased. Within each row, the source of each access transistor is coupled to a corresponding virtual ground line, and each capacitor structure is coupled to a corresponding word line. Alternately, the source of each access transistor in a column is coupled to a corresponding virtual ground line. Within each column, the drain of each access transistor is coupled to a corresponding bit line. Select memory cells in each row are programmed by band-to-band tunneling. Bit line biasing prevents programming of non-selected cells of the row. Programming is prevented in non-selected rows by controlling the well region voltages of these rows. Sector erase operations are implemented by Fowler-Nordheim tunneling.
    Type: Grant
    Filed: January 28, 2008
    Date of Patent: April 21, 2009
    Assignee: MoSys, Inc.
    Inventors: Gang-feng Fang, Wingyu Leung
  • Patent number: 7499307
    Abstract: A method and apparatus for scaling an embedded DRAM array from a first process to a second process, wherein the scaling involves reducing the linear dimensions of features by a constant scale factor. From the first process to the second process, DRAM cell capacitor layout area is reduced by the square of the scale factor, while cell capacitance is reduced by the scale factor. The voltage used to supply the logic transistors is scaled down from the first process to the second process. However, the voltage used to supply the sense amplifiers remains constant in both processes. Thus, in an embedded DRAM array of the second process, sense amplifiers are supplied by a greater voltage than the logic transistors. This allows the sensing voltage of DRAM cells to be maintained from one process generation to another, while allowing memory size to scale with the square of the process scale factor.
    Type: Grant
    Filed: September 22, 2006
    Date of Patent: March 3, 2009
    Assignee: MoSys, Inc.
    Inventor: Wingyu Leung
  • Patent number: 7477546
    Abstract: A non-volatile memory system including an array of cells, each having an access transistor and a capacitor sharing a floating gate. The access transistors in each row are fabricated in separate well regions, which are independently biased. Within each row, the source of each access transistor is coupled to a corresponding virtual ground line, and each capacitor structure is coupled to a corresponding word line. Alternately, the source of each access transistor in a column is coupled to a corresponding virtual ground line. Within each column, the drain of each access transistor is coupled to a corresponding bit line. Select memory cells in each row are programmed by band-to-band tunneling. Bit line biasing prevents programming of non-selected cells of the row. Programming is prevented in non-selected rows by controlling the well region voltages of these rows. Sector erase operations are implemented by Fowler-Nordheim tunneling.
    Type: Grant
    Filed: January 28, 2008
    Date of Patent: January 13, 2009
    Assignee: MoSys, Inc.
    Inventors: Gang-feng Fang, Wingyu Leung