Abstract: A memory device which utilizes a plurality of memory modules coupled in parallel to a master I/O module through a single directional asymmetrical signal swing (DASS) bus. This structure provides an I/O scheme having symmetrical swing around half the supply voltage, high through-put, high data bandwidth, short access time, low latency and high noise immunity. The device utilizes improved column access circuitry including an improved address sequencing circuit and a data amplifier within each memory module. A resynchronization circuit allows the device to operate either synchronously and asynchronously using the same pins. Each memory module has independent address and command decoders to enable independent operation so that each memory module is activated by commands on the DASS bus only when a memory access operation is performed within the particular memory module. Redundant memory modules are included to replace defective memory modules, and replacement can be carried out through commands on the DASS bus.

Abstract: A method is provided for operating a memory system having a plurality of memory blocks. The method includes (1) periodically asserting a timing signal; (2) asserting a refresh pending signal in each of the memory blocks when the asserted timing signal is received; (3) within each of the memory blocks, performing a refresh operation if the refresh pending signal in the memory block is asserted and an idle cycle exists in the memory block; (4) within each of the memory blocks, asserting a refresh acknowledge signal if a refresh operation is performed in the memory block; (5) within each of the memory blocks, de-asserting the refresh pending signal in the memory block if the refresh acknowledge signal is asserted in the memory block; (6) asserting a refresh forcing signal if the refresh pending signal in any of the memory blocks is asserted when the timing signal is asserted; and (7) forcing an idle cycle in all of the memory blocks if the refresh forcing signal is asserted.

Abstract: A method and apparatus for handling the refresh of a DRAM array or other memory array requiring periodic refresh operations so that the refresh does not require explicit control signaling nor handshake communication between the memory array and an external accessing client. The method and apparatus handles external accesses and refresh operations such that the refresh operations do not interfere with the external accesses under any conditions. As a result, an SRAM compatible device can be built from DRAM or 1-Transistor cells. A single-port multi-bank refresh scheme is used to cut down the number of collisions between memory refresh operations and memory data access operations. A read buffer is used to buffer read data, thereby allowing memory refresh operations to be performed when consecutive read accesses hit the address range of a particular memory bank for a long period of time.

Abstract: A method and structure for handling the refresh of a DRAM array so that the refresh has no effect on the external access. A system clock signal initiates activation and deactivation of elements of the DRAM array using a sequencer which subdivides each system clock signal period into three parts, thus providing four control signals fixed phase relationship per clock period.

Abstract: A memory system including a DRAM array, a read buffer, a write buffer and an input/output (I/O) interface. The read buffer and write buffer are coupled between the DRAM array and the I/O interface. When an external transaction involves multiple pieces of data in consecutive address locations, such as a burst access, parallel operations are performed in the DRAM array and the I/O interface. In a burst read transaction, all the data in the burst transaction is pre-fetched from the DRAM memory into the read buffer in one memory cycle. After the read data has been pre-fetched, the DRAM array is available for a refresh operation. The DRAM array can therefore be refreshed while the burst read data is sequentially transferred from the read buffer to the I/O interface. In a burst write transaction, multiple burst write data values are written to the write buffer over multiple I/O cycles. This burst write data is not retired to the DRAM array until the next write transaction.

Abstract: A memory system is provided that controls a memory that must be refreshed, such as DRAM, in a manner that does not require extensive external control. In one embodiment, the memory system includes a memory controller and a memory block that are coupled by a system bus. The memory block includes an array of memory cells that must be periodically refreshed to maintain valid data. The memory block also includes a refresh control circuit that refreshes the memory cells during idle cycles of the memory array. The memory controller monitors the number of idle cycles on the system bus during a predetermined refresh period. If the number of monitored idle cycles is less than a predetermined required number of idle cycles, the memory controller forces the required number of idle cycles on the system bus. As a result, the memory controller ensures that there will always be enough idle cycles in which the memory array can be refreshed.

Abstract: A graphics sub-system having a 2-D graphics accelerator, a 3-D graphics accelerator and an embedded DRAM memory. The embedded DRAM memory serves as a frame buffer memory and/or a temporary storage memory for the 2-D graphics accelerator. The embedded DRAM memory also serves as a cache memory for the 3-D graphics accelerator or an external central processing unit (CPU). The embedded DRAM memory is logically divided into a plurality of independent banks, thereby resulting in a relatively fast average memory cycle time. More specifically, the embedded DRAM memory processes one transaction per clock cycle for accesses with no bank conflicts. The memory access time for any transaction (e.g., a bank-conflict access) is no greater than the memory cycle time plus the memory access time minus 1 clock cycle.

Abstract: A memory system that includes a dynamic random access memory (DRAM) cell, a word line, and a CMOS word line driver fabricated using a conventional logic process. The word line driver is controlled to provide a positive boosted voltage and a negative boosted voltage to the word line, thereby controlling access to the DRAM cell. A positive boosted voltage generator is provided to generate the positive boosted voltage, such that this voltage is greater than V.sub.dd but less than V.sub.dd plus the absolute value of a transistor threshold voltage V.sub.t. Similarly, a negative boosted voltage generator is provided to generate a negative boosted voltage, such that this voltage is less than V.sub.SS by an amount less than V.sub.t. A coupling circuit is provided between the word line driver and one of the positive or negative boosted voltage generators. The coupling circuit couples the word line driver to the selected one of the positive or negative boosted word line generators only when the word line is activated.

Abstract: A structure for handling the refresh of a DRAM array so that the refresh has no effect on the external access. A system clock signal initiates activation and deactivation of elements of the DRAM array using a sequencer which subdivides each system clock signal period into three parts, thus providing four control signals fixed phase relationship per clock period.

Abstract: A method and structure for implementing a DRAM memory array as a second level cache memory in a computer system. The computer system includes a central processing unit (CPU), a first level SRAM cache memory, a CPU bus coupled to the CPU, and a second level cache memory which includes a DRAM array coupled to the CPU bus. When accessing the DRAM array, row access and column decoding operations are performed in a self-timed asynchronous manner. Predetermined sequences of column select operations are then performed in a synchronous manner with respect to a clock signal. A widened data path is provided to the DRAM array, effectively increasing the data rate of the DRAM array. By operating the DRAM array at a higher data rate than the CPU bus, additional time is provided for precharging the DRAM array. As a result, the precharging of the DRAM array is transparent to the CPU bus. A structure and method control the refresh and internal operations of the DRAM array.

Abstract: A method and structure for handling the refresh of a DRAM array so that the refresh has no effect on the external access. A system clock signal initiates activation and deactivation of elements of the DRAM array using a sequencer which subdivides each system clock signal period into three parts, thus providing four control signals fixed phase relationship per clock period.

Abstract: A structure which stores charge useful in a DRAM provides small cell size and eliminates subthreshold leakage current of the access transistor in the cell. Hence this is highly suitable for use for instance in ASICs (applications specific integrated circuits) which are fabricated using "logic" circuit fabrication techniques which normally do not accommodate DRAM cells. The DRAM charge storage structure includes a p-channel access transistor and an n-doped well in a p-doped substrate, a p-channel charge storage capacitor with its source/drain directly connected to the source region of the access field effect transistor, a source of a voltage to the gate of the storage capacitor, and a voltage source connected to the wordline and thereby to the gate terminal of the access transistor which switches between two voltage levels.

Abstract: A memory system including a DRAM array, a read buffer, a write buffer and an input/output (I/O) interface. The read buffer and write buffer are coupled between the DRAM array and the I/O interface. When an external transaction involves multiple pieces of data in consecutive address locations, such as a burst access, parallel operations are performed in the DRAM array and the I/O interface. In a burst read transaction, all the data in the burst transaction is pre-fetched from the DRAM memory into the read buffer in one memory cycle. After the read data has been pre-fetched, the DRAM array is available for a refresh operation. The DRAM array can therefore be refreshed while the burst read data is sequentially transferred from the read buffer to the I/O interface. In a burst write transaction, multiple burst write data values are written to the write buffer over multiple I/O cycles. This burst write data is not retired to the DRAM array until the next write transaction.

Abstract: A method and apparatus for handling the refresh of a DRAM array so that the refresh has no effect on the external access. This allows an SRAM compatible memory to be built from DRAM (or 1-Transistor) cells. By utilizing the unused external access time for performing the infrequent memory refresh, there is no penalty on the peak bandwidth requirement of the memory array.

Abstract: A method and apparatus for handling the refresh of a DRAM array or other memory array that requires periodic refresh operations. The method and apparatus handles external accesses and refresh operations such that the refresh operations do not interfere with the external accesses under any conditions. As a result, an SRAM compatible device can be built from DRAM or 1-Transistor cells. The apparatus includes a multi-bank DRAM memory and an SRAM cache that stores the most recently accessed data. Each of the DRAM banks is operated with independent control, thereby enabling parallel refresh operations and read-write accesses to different banks. The capacity of the SRAM cache is selected such that refresh operations can be carried out even under the condition of indefinite 100% access of the multi-bank DRAM memory.

Abstract: A structure and method of implementing a cache memory for a multi-processor system. The cache memory includes a main memory which is coupled to a main memory bus. A plurality of processors can also be coupled to the main memory bus. The main memory includes a plurality of RAM circuit module memory banks. The sense amplifiers of a predetermined number of banks are used as cache memory (i.e., sense amplifier cache lines). The number of banks used with sense amplifiers activated is substantially less than the total number of banks. The banks which are not used as cache memory are kept in a precharged state.

Abstract: Method and apparatus for refreshing DRAM devices (chips) in a computer system. Each DRAM device incorporates circuitry to carry out a burst of RAS cycles during each refresh period. Three different modes are used to trigger the device into refresh. In one mode, each DRAM device incorporates a refresh timer; only one master DRAM device in the system has its refresh timer enabled. The refresh master device generates a refresh request every time the refresh timer times up. A memory controller, after receiving the request, generates an acknowledge signal when certain system conditions are met. All DRAM devices in the system monitor the refresh request and acknowledge handshake continuously. Upon detection of refresh acknowledge, each DRAM device caries out a sequence of predesignated refresh cycles.

Abstract: A multi-port DRAM cell structure that enables read, write and refresh accesses at each port of the DRAM cell. The DRAM cell includes a storage capacitor for storing a data value, and a plurality of ports for accessing the storage capacitor. Each port enables both read and write accesses to the storage capacitor. Each port can include a port access transistor, a port bitline and a port wordline. The port access transistor includes a gate electrode, a source and a drain. The source of the port access transistor is coupled to the storage capacitor, the drain of the port access transistor is coupled to the port bitline, and the gate electrode of the port access transistor is coupled to the port wordline. This cell architecture enables overlapping read and write accesses to be simultaneously performed at the various ports of the multi-port DRAM cell.

Abstract: A system and method for wafer scale integration optimized for medium die size integrated circuits by interconnecting a large number of separate memory (or other circuit) modules on a semiconductor wafer so as to electrically exclude both defective modules and defective interconnect/power segments, and include operative modules and interconnect/power segments. A set of discretionary connections are associated with each of the separate modules and interconnect/power segments and such connections are made (or broken) after a module or interconnect or power segment is tested. A power supply network is set up by combining operative power segments. A bidirectional bus is set up by combining operative interconnect segments to connect to each operative modules. This bidirectional bus consists of one or more hierarchies for speed, power and yield considerations. Each module is assigned an identity code using discretionary connections.

Abstract: A bus line termination circuit for limiting signal swing on a bus line to a reduced CMOS-swing. The termination circuit includes a switch and a first resistor connected in series between the bus line and a first voltage supply, and a second resistor connected in series between the bus line and a second voltage supply. The values of the first and second resistors are selected such that a termination voltage equal to the average of the first and second supply voltages exists on the bus line. The bus line is further connected to a receiver circuit having a threshold voltage equal to the average of the first and second supply voltages. The switch is controlled to disconnect the bus line from the first voltage supply when the bus line is in an inactive state. In an alternative embodiment, a termination circuit includes one or more voltage regulator circuits, each being coupled to the first and second voltage supplies. A clamping resistor coupled each voltage regulator circuit to the bus line.