Patents by Inventor Winston Ki-Cheong Mok

Winston Ki-Cheong Mok has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7417985
    Abstract: A method and an apparatus for reducing power consumption and digital logic noise in a time division multiplexed memory switch. The method is embodied in an egress selection switch (ESS) block architecture. The ESS block includes a data disable block which prevents the propagation of data, in particular ingress grains, to a given group of egress ports if the data is not selected by any of the egress ports in a given group. While the ingress data disable method partitions ports into groups and saves power by disabling the fanout tree from the root on a port group basis, the egress data disable method saves power on a port group basis by disabling the fanout tree from the tail end in addition to applying the ingress data disable method. The ESS block also includes an grain select block for selecting and storing a given ingress grain for eventual output to an egress port.
    Type: Grant
    Filed: January 29, 2004
    Date of Patent: August 26, 2008
    Assignee: PMC-Sierra, Inc.
    Inventors: Carl Dietz McCrosky, Andrew Milton Hughes, Winston Ki-Cheong Mok, Nick Rolheiser
  • Patent number: 6333935
    Abstract: A plurality of time-division multiplexed data streams which are merged into a single data stream containing a plurality of data words and which are characterized by state vectors, are concurrently processed. The state vectors are stored in a read-write memory having a plurality of addressable memory locations. During an initial clock cycle, a pipeline receives an input data word from one of the data streams, an input state vector characterizing that data stream, and the memory location address of the input state vector. During one or more intermediate clock cycles, the pipeline processes the input data word and the input state vector to yield an output data word and an output state vector. During a final clock cycle, the pipeline transfers the output data word to an outgoing data stream, and transfers the output state vector into the aforementioned memory location address. A controller coupled to the memory and to the pipeline synchronizes operation thereof.
    Type: Grant
    Filed: April 9, 1998
    Date of Patent: December 25, 2001
    Assignee: PMC-Sierra Ltd.
    Inventors: Larrie Simon Carr, Winston Ki-Cheong Mok
  • Patent number: 6188699
    Abstract: A multi-channel network device for interfacing between a plurality of physical data links and a control processor, where each physical data link is characterized by a data stream of data packets communicated according to a data link control protocol. The multi-channel network device includes a plurality of receive-side line interfaces, with each with each receive-side line interface having at least one channel associated therewith. Each receive-side line interface is operative to receive incoming data packets from one of the physical data links such that each incoming data packet is received in at least one incoming data segment. Each receive-side line interface is also operative to determine a time-slot number for each incoming data segment arriving thereon.
    Type: Grant
    Filed: December 11, 1997
    Date of Patent: February 13, 2001
    Assignee: PMC-Sierra Ltd.
    Inventors: Steven Forbes Lang, Winston Ki-Cheong Mok, Larrie Simon Carr, Richard Arthur John Steedman, Glenn Kenneth Bindley