Abstract: A method for testing wireless communication devices in stages in a production line for the assembly of said devices, comprises assembling each respective wireless communication device such that each device includes an interactive test component for interactively testing the device; and testing each device using the interactive test component at an interactive test stage of the production line. The testing maybe performed at the interactive test stage without an external test system. A test result may be stored to the device for storing to an external testing database at a subsequent testing stage and for controlling the performing of subsequent testing.

Abstract: A time:space:time switch fabric incorporating an odd integer number of spatially distributed data switches and a plurality of spatially distributed data serializers. Each data switch has a first plurality of ingress ports, an equal plurality of egress ports, and a space switch for selectably interconnecting any one of the ingress ports to any one of the egress ports. Each data serializer has an input bus for receiving signals to be routed through the switch fabric, an output bus for outputting signals routed through the switch fabric, a plurality of egress ports selectably connectible to any one of the data switch ingress ports, and an equal plurality of ingress ports selectably connectible to any one of the data switch egress ports.

Abstract: Pointer justification event induced low frequency jitter is attenuated during desynchronization of a synchronous input data stream into a plesiosynchronous output data stream. The output data stream has a clock rate T and is made up of tb byte multi-frames containing a nominal number tdb of data bits (tdb=772 and tb=104 for T1 data; tdb=1024 and tb=140 for E1 data). An integer number pc of phase adjustment commands are provided (in the preferred embodiment, pc=12 for T1 data and pc=9 for E1 data). A count having a total value pjT, where 1≦pjT≦tb, is maintained of the total number of positive pointer justification events previously encountered in the data stream. A separate count having a total value pcT, where 1≦pcT≦tdb*pc, is maintained of the total number of previously issued phase adjustment commands. If a positive pointer justification event is detected in the data stream, pjT is incremented by one.

Abstract: This document discloses some technical details of a FIFO interface used for both cell and packet data transfer. This interface is suitable for a large number of ports. It operates at an overall throughput of 800 Mb/s for 16-bit wide data paths at 50 MHz, and 3.2 Gb/s for 32-bit wide data paths at 100 MHz. It is designed to have minimal compatibility issues with UTOPIA L2 and similar interfaces.

Abstract: A POS-PHY interface for interfacing between SONET/SDH PHY devices and Link Layer devices, including a 32 bit and an 8-bit point-to-point bus interface having a double-word data format operative to accommodate variable size packets of packet data.

Abstract: A scaleable bandwidth interconnect (SBI) for interconnection of physical layer devices with link layer devices which includes an ADD BUS interface operative to receive data from one of the link layer devices and direct it to one of the physical layer devices and a DROP BUS interface operative to receive data from one of the physical layer devices and direct it to one of the link layer devices. By utilizing buses to access each of the physical layer devices and the link layer devices permits interfacing between a high density of physical layer devices and a high density of link layer devices.

Abstract: A method of interfacing for packet and cell transfer between a first layer device and a second layer device, which includes dividing control information into an in-band portion and an out-of-band portion, transmitting the in-band portion in the data path, and transmitting the out-of-band portion outside of the data path.

Abstract: A time:space:time switch fabric incorporating an odd integer number of spatially distributed data switches and a plurality of spatially distributed data serializers. Each data switch has a first plurality of ingress ports, an equal plurality of egress ports, and a space switch for selectably interconnecting any one of the ingress ports to any one of the egress ports. Each data serializer has an input bus for receiving signals to be routed through the switch fabric, an output bus for outputting signals routed through the switch fabric, a plurality of egress ports selectably connectible to any one of the data switch ingress ports, and an equal plurality of ingress ports selectably connectible to any one of the data switch egress ports.

Abstract: A parallel to serial converter comprising a parallel word latch for receiving a series of words comprised of parallel data words, a shift register for receiving the parallel data words and for storing bits of a parallel data word in a series of shift register stages upon receipt of a first enable signal, and for providing a serial stream of bits at a serial clock rate, a circuit for receiving a serial clock signal and for providing the serial clock signal to the shift register to enable shifting of the stored bits to an output as the serial stream of bits, and a controller for generating the enable signal and for applying the enable signal to the shift register and parallel word latch, said controller being comprised of a counter for counting input clock pulses at a serial bit rate and for providing the enable signal upon counting plural input clock pulses, the counter being comprised of active elements restricted to plural combination multiplexed flip/flops.

Abstract: A serial to parallel converter comprising a serial shift register for receiving an incoming serial stream of bits, a parallel word latch for receiving in parallel bits stored by the shift register, when enabled by an enable signal at an enable time, and for providing a parallel data output signal, a controller for generating an enable signal at the enable time and applying the enable signal to the parallel word latch, the controller being comprised of a counter for counting input clock pulses at a serial bit rate and for providing the enable signal upon counting plural input clock pulses, the counter being comprised of active elements restricted to plural combination multiplexed flip/flops.

Abstract: A plurality of data streams time-division multiplexed into a single stream are concurrently processed. State vectors characteristic of each data stream are stored in unique read-write memory locations having known addresses. During an initial clock cycle the next sequential data word is received from the single data stream and an input state vector characteristic of the data stream in which the received data originated is retrieved from the memory. The data word and the input state vector are passed to state machine logic which, during one or more intermediate clock cycles, processes the data word and the input state vector to produce an output data word and an output state vector. During a final clock cycle the output data word is transferred to an outgoing data stream and the output state vector is stored in the memory location from which the input state vector was retrieved.