Abstract: A method for low-level security based on the UID. In particular it enhances an RFID system by adding the ability to dynamically modify the UID of the smartcard or to randomly generate a new UID for the smartcard.

Abstract: A smartcard having a microcontroller kernel and a non-secure memory capable of storing a Random-ID code, where the non-secure memory is electrically coupled to the microcontroller kernel. A random number generator is for generating a new Random-ID code and the random number generator is electrically coupled to the microcontroller kernel. A user interface is electrically coupled to the random number generator so that the user may initiate generation of the new Random-ID code by the random number generator for storage in the non-secure memory.

Abstract: A smartcard having a microcontroller kernel and a non-secure memory capable of storing a Random-ID code, where the non-secure memory is electrically coupled to the microcontroller kernel. A random number generator is for generating a new Random-ID code and the random number generator is electrically coupled to the microcontroller kernel. A user interface is electrically coupled to the random number generator so that the user may initiate generation of the new Random-ID code by the random number generator for storage in the non-secure memory.

Abstract: The invention relates to an integrated circuit card (1) comprising: an input/output block (4) for receiving external command data from an interface device (2); a central processing unit (CPU) (3) in signal communication with the input/output block (4) for performing a task corresponding to the received command data; a judgement block (5) in signal communication with the central processing unit (3) for judging whether a working time of the central processing unit (3) reaches a reference time, after an input of the external command data is completed; and a control block (6) in signal communication with the judgement block (5) for operating responsive to an output of the judgement block, wherein the control block controls such that a S(WTX request) is output via the input/output block (4) without intervention by the central processing unit whenever the interface device (2) connected to the integrated circuit card (1) transmits a command to the integrated circuit card and the integrated circuit card is not able t

Abstract: An apparatus and method is provided for protecting data in a non-volatile memory by using an encryption and decryption that encrypts and decrypts the address and the data stored in the non-volatile memory using a code read only memory that stores encryption and decryption keys that are addressed by a related central processing unit at the same time data is being written or read from the non-volatile memory by the central processing unit.

Abstract: A communication pad for communication with a communication terminal is provided, wherein the communication pad comprises a processing unit and a non-volatile memory having a crypto key and/or a unique identification code stored thereon, wherein the processing unit is adapted to process the crypto key together with authentication challenge data to generate an authentication response, and wherein the communication pad is adapted to be identified to the communication terminal by sending the authentication response and/or a unique identification code to the communication terminal. In particular, the communication pad may be a user proprietary game pad, adapted to communicate with an open domain stand-alone or network-based game terminal.

Abstract: The invention relates to an integrated circuit card (1) comprising: an input/output block (4) for receiving external command data from an interface device (2); a central processing unit (CPU) (3) in signal communication with the input/output block (4) for performing a task corresponding to the received command data; a judgement block (5) in signal communication with the central processing unit (3) for judging whether a working time of the central processing unit (3) reaches a reference time, after an input of the external command data is completed; and a control block (6) in signal communication with the judgement block (5) for operating responsive to an output of the judgement block, wherein the control block controls such that a S(WTX request) is output via the input/output block (4) without intervention by the central processing unit whenever the interface device (2) connected to the integrated circuit card (1) transmits a command to the integrated circuit card and the integrated circuit card is not able t

Abstract: In order to further develop a circuit arrangement (100) as well as a method of processing data to be protected against unauthorized access by means of encryption or decryption, by means of which method the data are stored in at least two memory modules (10, 12) in such way that a flexible configuration of any memory parts as main memory or redundancy memory is enabled, it is proposed to provide at least one real-time configurable redundancy concept for the memory modules (10, 12), by which the data can be stored redundantly in physically separate memory modules (10, 12).

Abstract: An apparatus and method is provided for protecting data in a non-volatile memory by using an encryption and decryption that encrypts and decrypts the address and the data stored in the non-volatile memory using a code read only memory that stores encryption and decryption keys that are addressed by a related central processing unit at the same time data is being written or read from the non-volatile memory by the central processing unit.

Abstract: In order to further develop a circuit arrangement (100), in particular an integrated circuit, for electronic data processing as well as a method for detecting and/or for registering and/or for signaling the irradiation of at least one non-volatile memory module (10) with at least one light source in order to be capable of securely averting an attack, in particular an E[lectro]M[agnetic] radiation attack, for example a side-channel attack, or in particular a crypto-analysis, for example a current trace analysis or a D[ifferential]P[ower]A[nalysis], such attack or such analysis in particular being targeted on finding out a private key, it is proposed that an access timing for at least one read access to the memory module (10) is generated, in particular that at least one additional read access to the memory module (10) is added in at least one test mode (T), in particular in at least one D[isable]A[ll]W[ordline] mode, this test mode (T) preferably allowing to detect if the memory module (10) is currently expose

Abstract: The invention describes a method and an arrangement for writing to NV memories in a controller architecture, together with a corresponding computer program product and a corresponding computer-readable storage medium, which may be used in particular to speed up writing or programming processes in NV code memories of microcontrollers, such as for example smart card controllers. The method consists in extending the instruction set of the controller by so-called MOVCWR (move code write) instructions, which make it possible to write a defined data word (byte) to a defined destination address within an NV code memory. The data word (byte) is here written to the correct position of the cache page register of the respective NV memory and the page address pointer register of the memory is updated with the associated page address. If an MMU (memory management unit) is present, this MOVCWR writing to the cache page register takes place, like MOVC reading or code fetch, under the control of this MMU.

Abstract: An apparatus and method is provided for protecting data in a non-volatile memory by using an encryption and decryption that encrypts and decrypts the address and the data stored in the non-volatile memory using a code read only memory that stores encryption and decryption keys that are addressed by a related central processing unit at the same time data is being written or read from the non-volatile memory by the central processing unit.

Abstract: In order to further develop a circuit arrangement (100) for electronic data communication, comprising—at least a non-volatile memory module (10) for storing data, and—at least an interface logic (20) associated with the memory module (10)—for addressing the memory module (10) and—for writing data to the memory module (10) or—for reading data from the memory module (10), together with a related method for registering light attacks on the non-volatile memory module (10), in such a way that, firstly, the light attack is recognized immediately and reliably regardless of whether an access, in particular a read access, to the memory module (10) is taking place or not and, secondly, the entire address space of the memory module (10) is covered as uniformly as possible in this regard, it is proposed that at least a monitoring arrangement (22) provided for monitoring the memory module (10) is associated with the interface logic (20), by means of which monitoring arrangement (22) an irradiation of the memory module (10

Abstract: In order to develop an electronic memory component or memory module (100), having at least one memory cell area (10) in which physical states (P) representing regular data are mapped by means of at least one mapping function (A) that describes at least one error correction code, for example at least one Hamming code, and also a method of operating at least one electronic memory component or memory module (100) of the abovementioned type, such that on the one hand the error detection probability is considerably increased and on the other hand unwritten memory blocks can be reliably distinguished from memory blocks that have already been written to once before, it is proposed that at least one further physical state in the form of at least one exceptional or special state (L, S) in the error correction code can be detected, encoded and/or indicated by means of the mapping function (A).

Abstract: In order further to develop a circuit arrangement (100) for electronic data processing—having at least one non-volatile memory module (10) for storing data to be protected against unauthorized access by means of encryption or decryption;—having at least one memory module interface logic circuit (12) assigned to the memory module (10)—for addressing the memory module (10) and —for writing the data to the memory module (10) or —for reading out the data from the memory module (10);—having at least one code R[ead]O[nly]M[emory] module (20) for storing and/or supplying at least one R[ead]O[nly]M[emory] code; and—having at least one code ROM module interface logic circuit (22) assigned to the code ROM module (20)—for addressing the code ROM module (20) and—for reading out the ROM code from the code ROM module (20) and an en-/decryption method based thereon in such a way that on the one hand the key code may be changed for different controller versions with different ROM codes and on the other hand the length of the

Abstract: In order to further develop a circuit arrangement (100) for electronic data communication, comprising—at least a non-volatile memory module (10) for storing data, and—at least an interface logic (20) associated with the memory module (10)—for addressing the memory module (10) and—for writing data to the memory module (10) or—for reading data from the memory module (10), together with a related method for registering light attacks on the non-volatile memory module (10), in such a way that, firstly, the light attack is recognized immediately and reliably regardless of whether an access, in particular a read access, to the memory module (10) is taking place or not and, secondly, the entire address space of the memory module (10) is covered as uniformly as possible in this regard, it is proposed that at least a monitoring arrangement (22) provided for monitoring the memory module (10) is associated with the interface logic (20), by means of which monitoring arrangement (22) an irradiation of the memory module (10

Abstract: The invention describes a method and an arrangement for writing to NV memories in a controller architecture, together with a corresponding computer program product and a corresponding computer-readable storage medium, which may be used in particular to speed up writing or programming processes in NV code memories of microcontrollers, such as for example smart card controllers. The method consists in extending the instruction set of the controller by so-called MOVCWR (move code write) instructions, which make it possible to write a defined data word (byte) to a defined destination address within an NV code memory. The data word (byte) is here written to the correct position of the cache page register of the respective NV memory and the page address pointer register of the memory is updated with the associated page address. If an MMU (memory management unit) is present, this MOVCWR writing to the cache page register takes place, like MOVC reading or code fetch, under the control of this MMU.

Abstract: The invention relates to a method and arrangement for programming and verifying EEPROM pages and a corresponding computer software product and a corresponding computer-readable storage medium, which can be used in particular to speed up the programming into the EEPROM of large amounts of data or code, such as occurs for example when smart cards are being personalized. The invention relates to an arrangement that sets up a DMA connection between EEPROM and RAM—not including the core of the microcontroller involved—and makes possible automatic programming of data blocks of random length from the RAM to the EEPROM including the verification of the programming operation against the original data in the RAM under the control of the EEPROM logic.

Abstract: To refine both an electrical or electronic circuit arrangement whose physical layout (100) comprises conductors (10) and cells (30, 40) associated with the conductors (10), such as flip-flop cells, buffer cells, inverter cells, logic gate cells or the like, and a method of generating at least one clock tree for the physical layout (100) of an electrical or electronic circuit arrangement, and to refine them in such a way that, when the clock tree is being adjusted, there is no need for the topology of any of the other cells outside the clock tree to be altered, it is proposed that the cells (30, 40) intended for the adjustment of the clock tree in the layout (100) be of a substantially uniform topological extent or size.

Abstract: To provide an electric or electronic circuit arrangement as well as a method of detecting and/or identifying and/or recording at least an access violation, particularly at least a memory access violation, in a microcontroller provided particularly for a chip card or smart card, with which the source causing this access violation (referred to as break source) as well as the code address occurring upon this violation can be detected and/or identified and/or recorded when an access violation occurs during the program run, the circuit arrangement comprises at least a memory unit; at least an interface unit assigned to the memory unit; at least a processor unit connected to the memory unit particularly via the interface unit for executing instruction codes.