Abstract: The invention relates to a method of dual-stage scrambling of addresses (LogAdr) with which a central processor (10) accesses a memory (13). A first encryption logic (11) applies a fixed, unchangeable key (KEY1), whereas a second encryption logic (12) applies a changeable second key (KEY2) stored in the memory (13). The configuration data written during the initialization phase of the central processor (10) are preferably stored in a special configuration range which is accessed via a bypass (15) while bypassing the second encryption logic (12). The bypass is activated by a bypass logic (14) which compares the addresses (Cipher 1) encrypted in the first stage with values (SecRowCipher1, SecRowCipher2) stored during the initialization phase.

Abstract: A description is given of a circuit arrangement for electronic data processing which includes a writeable memory for storing data to be protected against unauthorized access, a read-only memory for storing individualizing data, a control unit for generating given control signals in dependence on a reset signal sequence to be executed by the control unit during operation of the circuit arrangement, a scrambling pattern generator for generating scrambling pattern signals by combining at least a part of the individualizing data from the read-only memory with the control signals during the execution of the reset signal sequence and for subsequently outputting these scrambling pattern signals until the execution of a next reset sequence, and a scrambling logic unit for the scrambling of address and/or data signals of the data to be stored in the writeable memory in conformity with the scrambling pattern signals supplied by the scrambling pattern generator upon storage of this data, and for the corresponding descra

Abstract: To refine both an electrical or electronic circuit arrangement whose physical layout (100) comprises conductors (10) and cells (30, 40) associated with the conductors (10), such as flip-flop cells, buffer cells, inverter cells, logic gate cells or the like, and a method of generating at least one clock tree for the physical layout (100) of an electrical or electronic circuit arrangement, and to refine them in such a way that, when the clock tree is being adjusted, there is no need for the topology of any of the other cells outside the clock tree to be altered, it is proposed that the cells (30, 40) intended for the adjustment of the clock tree in the layout (100) be of a substantially uniform topological extent or size.

Abstract: The invention relates to a method and arrangement for programming and verifying EEPROM pages and a corresponding computer software product and a corresponding computer-readable storage medium, which can be used in particular to speed up the programming into the EEPROM of large amounts of data or code, such as occurs for example when smart cards are being personalized.

Abstract: To provide an electric or electronic circuit arrangement (100) as well as a method of detecting and/or identifying and/or recording at least an access violation, particularly at least a memory access violation, in a microcontroller provided particularly for a chip card or smart card, with which the source causing this access violation (referred to as break source) as well as the code address occurring upon this violation can be detected and/or identified and/or recorded when an access violation occurs during the program run, the circuit arrangement comprises

Abstract: In order to unambiguously allocate a data carrier to an object, key information is written into the data carrier. Before writing-in the key information, secret identification information and open identification information is written into the data carrier. Copies of the secret and open information are stored in a central station. In the central station, for a particular data carrier, the open and secret information is associated with each other. In addition thereto, in the central station, object information for the particular object, and key information for the object are associated with each other. From the data carrier, the open identification information is sent to the central station to access the associated stored open and secret identification information so as to retrieve the stored secret identification information. In addition thereto, object information is sent to the central station to access the associated stored object and key information so as to retrieve the stored key information.

Abstract: In the case of keys which cooperate electronically with an object, for example a motor vehicle, it is often necessary to produce a new key. These keys must be available rapidly at remote locations, so that the object-specific key information must be transmitted and written into the key in a secure manner. For this purpose, according to the invention, object information is transmitted from the remote station to a central station, which reads out the key information stored for this purpose and encrypts it with identification information stored both in the central station and in the key and transmits this to the key. By means of the secret identification information stored therein the key is capable of recovering and storing the original key information.

Abstract: A circuit arrangement for the display of a cursor symbol of variable magnitude addresses the cursor memory by means of a separate addressing device which operates only during display of the cursor field. The organization of the memory for the cursor symbol, constructed as a matrix memory, is fully independent of the rows and columns of the cursor field, i.e. to the cursor symbol the memory appears as a pure linear memory. As a result, this memory can be utilized in a substantially improved manner and the display of even large cursor symbols requires only a limited storage capacity.