Abstract: The invention relates to a sense amplifier for sensing and amplifying data stored in a memory cell, the sense amplifier being connected between a bit line (BL) and a reference bit line complementary (/BL) to the first bit line and comprising: a sense circuit (SC) capable of providing an output indicative of the data stored in the memory cell; and a precharge and decode circuit (PDC) comprising a pair of dual gate transistors (T5, T6) for precharging the first and second bit lines during a precharge operation and for transferring the output provided by the sense circuit to a data line (LIO,/LIO) during a read operation.

Abstract: The invention relates to a sense amplifier for sensing and amplifying data stored in a memory cell, the sense amplifier being connected between a bit line (BL) and a reference bit line complementary (/BL) to the first bit line and comprising: a sense circuit (SC) capable of providing an output indicative of the data stored in the memory cell; and a precharge and decode circuit (PDC) comprising a pair of dual gate transistors (T5, T6) for precharging the first and second bit lines during a precharge operation and for transferring the output provided by the sense circuit to a data line (LIO,/LIO) during a read operation.

Abstract: The present invention relates to a method for the manufacture of a semiconductor device by providing a first substrate; providing a doped layer in a surface region of the first substrate; providing a buried oxide layer on the doped layer; providing a semiconductor layer on the buried oxide layer to obtain a semiconductor-on-insulator (SeOI) wafer; removing the buried oxide layer and the semiconductor layer from a first region of the SeOI wafer while maintaining the buried oxide layer and the semiconductor layer in a second region of the SeOI water; providing an upper transistor in the second region by forming a back gate in or by the doped layer; and providing a lower transistor in the first region by forming source and drain regions in or by the doped layer.

Abstract: The present invention relates to a method for the manufacture of a semiconductor device by providing a first substrate; providing a doped layer in a surface region of the first substrate; providing a buried oxide layer on the doped layer; providing a semiconductor layer on the buried oxide layer to obtain a semiconductor-on-insulator (SeOI) wafer; removing the buried oxide layer and the semiconductor layer from a first region of the SeOI wafer while maintaining the buried oxide layer and the semiconductor layer in a second region of the SeOI water; providing an upper transistor in the second region by forming a back gate in or by the doped layer; and providing a lower transistor in the first region by forming source and drain regions in or by the doped layer.

Abstract: The invention relates to a vertical integrated component, a component arrangement and a method for production of a vertical integrated component. The vertical integrated component has a first electrical conducting layer, a mid layer, partly embodied from dielectric material on the first electrical conducting layer, a second electrical conducting layer on the mid layer and a nanostructure integrated in a through hold introduced in the mid layer. A first end section of the nanostructure is coupled to the first electrical conducting layer and a second end section is coupled to the second electrical conducting layer. The mid layer includes a third electrical conducting layer between two adjacent dielectric partial layers, the thickness of which is less than the thickness of at least one of the dielectric partial layers.

Abstract: A method for producing a microelectronic structure is suggested in which a layer structure (30) which partially covers a substrate (5) and which comprises at least one first conductive layer (15,20) which reaches to a side wall (35) of the layer structure (30), is covered with a second conductive layer (45). The second conductive layer (45) is then subsequently back-etched to as great an extent as possible with an etching process with physical delamination, wherein delaminated material deposits on the side wall (35) of the layer structure (30). On the side wall (35) the delaminated material forms a protection layer (60) by means of which the first conductive layer (15,20) is to be protected from attack by oxygen to the furthest extent possible.

Abstract: An arrangement and process for producing a circuit arrangement is disclosed. The process includes having a layer arrangement, in which two electrically conductive interconnects running substantially parallel to one another are formed on a substrate. At least one auxiliary structure is formed on the substrate and between the two interconnects, running in a first direction, which first direction includes an angle of between 45 degrees and 90 degrees with a connecting axis of the interconnects, running orthogonally with respect to the two interconnects, the at least one auxiliary structure being produced from a material which allows the at least one auxiliary structure to be selectively removed from a dielectric layer. The dielectric layer is formed between the two interconnects, in such a manner that the at least one auxiliary structure is at least partially covered by the dielectric layer.

Abstract: The invention provides in a preferred embodiment an electronic component comprising a first conductive layer, a non-conductive layer and a second conductive layer. A hole is etched through the non-conductive layer. A nanotube, which is provided in said hole, links the first conductive layer to the second conductive layer in a conductive manner.

Abstract: A multiplicity of nanotubes are applied to at least one external chip metal contact of an electronic chip in order to make contact between the electronic chip and a further electronic chip.

Abstract: An integrated circuit having a multilayer capacitance arrangement and a method for producing an integrated circuit having a multilayer capacitance arrangement are disclosed.

Abstract: A nonvolatile memory cell, memory cell arrangement, and method for production of a nonvolatile memory cell is disclosed. The nonvolatile memory cell includes a vertical field-effect transistor (FET). The FET contains a nanoelement arranged as a channel region and an electrically insulating layer. The electrically insulating layer at least partially surrounds the nanoelement and acts as a charge storage layer and as a gate-insulating layer. The electrically insulating layer is arranged such that electrical charge carriers may be selectively introduced into or removed from the electrically insulating layer and the electrical conductivity characteristics of the nanoelement may be influenced by the electrical charge carriers introduced into the electrically insulating layer.

Abstract: A low temperature CVD process for deposition of bismuth-containing ceramic thin films suitable for integration to fabricate ferroelectric memory devices. The bismuth-containing film can be formed using a tris(?-diketonate) bismuth precursor. Films of amorphous SBT can be formed by CVD and then ferroannealed to produce films with Aurivillius phase composition having superior ferroelectric properties suitable for manufacturing high density FRAMs.

Abstract: The state is read out from the ferroelectric transistor or stored in the ferroelectric transistor. During the read-out or storage of the state, at least one further ferroelectric transistor in the memory matrix is driven in such a way that it is operated in its depletion region.

Abstract: The state of a ferroelectric transistor in a memory cell is read or stored, and the threshold voltage of further ferroelectric transistors in further memory cells in the memory matrix is increased during the reading or storing, or is increased permanently. A memory configuration including ferroelectric memory cells is also provided.

Abstract: A low temperature CVD process for deposition of bismuth-containing ceramic thin films suitable for integration to fabricate ferroelectric memory devices. The bismuth-containing film can be formed using a tris(&bgr;-diketonate) bismuth precursor. Films of amorphous SBT can be formed by CVD and then ferroannealed to produce films with Aurivillius phase composition having superior ferroelectric properties suitable for manufacturing high density FRAMs.

Abstract: A field-effect transistor that having a nanowire, which forms a source region, a channel region and a drain region of the field-effect transistor, the nanowire being a semiconducting and/or metallically conductive nanowire. The field-effect transistor also has at least one nanotube, which forms a gate region of the field-effect transistor, the nanotube being a semiconducting and/or metallically conductive nanotube. The nanowire and the nanotube are arranged at a distance from one another or set up in such a manner that it is substantially impossible for there to be a tunneling current between the nanowire and the nanotube, and that the conductivity of the channel region of the nanowire can be controlled by means of a field effect as a result of an electric voltage being applied to the nanotube.

Abstract: A low temperature CVD process using a tris (&bgr;-diketonate) bismuth precursor for deposition of bismuth ceramic thin films suitable for integration to fabricate ferroelectric memory devices. Films of amorphous SBT can be formed by CVD and then ferroannealed to produce films with Aurivillius phase composition having superior ferroelectric properties suitable for manufacturing high density FRAMs.

Abstract: A ferroelectric transistor suitable as a memory element has a first gate intermediate layer and a first gate electrode disposed on the surface of a semiconductor substrate and disposed between source/drain regions. The first gate intermediate layer contains at least one ferroelectric layer. In addition to the first gate intermediate layer, a second gate intermediate layer and a second gate electrode are configured between the source/drain regions. The second gate intermediate layer contains a dielectric layer. The first gate electrode and the second gate electrode are connected to each other via a diode structure.

Abstract: A method for producing a microelectronic structure is suggested in which a layer structure (30) which partially covers a substrate (5) and which comprises at least one first conductive layer (15,20) which reaches to a side wall (35) of the layer structure (30), is covered with a second conductive layer (45). The second conductive layer (45) is then subsequently back-etched to as great an extent as possible with an etching process with physical delamination, wherein delaminated material deposits on the side wall (35) of the layer structure (30). On the side wall (35) the delaminated material forms a protection layer (60) by means of which the first conductive layer (15,20) is to be protected from attack by oxygen to the furthest extent possible.

Abstract: A capacitor for a semiconductor configuration and a method for producing a dielectric layer for the capacitor. The dielectric layer consists of cerium oxide, zirconium oxide, hafnium oxide or various films of the materials.