Abstract: A resistor cascade has a multiplicity of electrical resistors connected in series, and each electrical resistor has at least one single-walled carbon nanotube.

Abstract: The crystallization temperature of a ferroelectric layer (3) (dielectric) for a storage capacitor can be lowered by applying a very thin (CeO2 layer (2) to a first platinum electrode layer (1) of the storage capacitor before the ferroelectric layer is deposited. The dielectric layer (3) deposited in amorphous state is then crystallized by a temperature treatment step at a temperature in the range between 590° C. and 620° C. A second electrode layer (4) is then applied to complete the storage capacitor.

Abstract: A resistor cascade has a multiplicity of electrical resistors connected in series, and each electrical resistor has at least one single-walled carbon nanotube.

Abstract: The invention relates to a multiwall nanotube having an outer wall and at least one inner wall, in which only the outer wall is oxidized and the inner wall or walls is/are not oxidized.

Abstract: An integrated circuit configuration, in particular is a DRAM cell configuration, includes a capacitor disposed on a first substrate and a portion with a contact disposed on a second substrate. The first substrate is connected to the second substrate, with the contact adjoining the capacitor. The first substrate and the second substrate can be connected essentially in an unadjusted manner, if capacitor elements are distributed over the first substrate and a contact surface of the contact is so large that when the substrates are connected, the contact in each case adjoins at least one of the capacitor elements, which then defines the capacitor. The capacitor may include a plurality of capacitor elements, which makes its capacitance especially high. A method is also provided for producing the integrated circuit configuration.

Abstract: The crystallization temperature of a ferroelectric layer (3) (dielectric) for a storage capacitor can be lowered by applying a very thin CeO2 layer (2) to a first platinum electrode layer (1) of the storage capacitor before the ferroelectric layer is deposited. The dielectric layer (3) deposited in amorphous state is then crystallized by a temperature treatment step at a temperature in the range between 590° C. and 620° C. A second electrode layer (4) is then applied to complete the storage capacitor.

Abstract: A low temperature CVD process using a tris (&bgr;-diketonate) bismuth precursor for deposition of bismuth ceramic thin films suitable for integration to fabricate ferroelectric memory devices. Films of amorphous SBT can be formed by CVD and then ferroannealed to produce films with Aurivillius phase composition having superior ferroelectric properties suitable for manufacturing high density FRAMs.

Abstract: The integrated semiconductor memory configuration has a semiconductor body in which selection transistors and storage capacitors are integrated. The storage capacitors have a dielectric layer configured between two electrodes. At least the upper electrode is constructed in a layered manner with a platinum layer, that is seated on the dielectric layer, and a thicker, base metal layer lying above the platinum layer.

Abstract: A low temperature CVD process using a tris (&bgr;-diketonate) bismuth precursor for deposition of bismuth ceramic thin films suitable for integration to fabricate ferroelectric memory devices. Films of amorphous SBT can be formed by CVD and then ferroannealed to produce films with Aurivillius phase composition having superior ferroelectric properties suitable for manufacturing high density FRAMs.

Abstract: A manufacturing method for a capacitor in an integrated memory circuit includes initially depositing a first conducting layer and an auxiliary layer acting as an etch-stop onto a carrier. Then a layer sequence which contains alternating layers of the first material and a second material is produced on top of the first conducting layer and the auxiliary layer. The layer sequence may, in particular, have p+/p− silicon layers or silicon/germanium layers. A layer structure with a base of a capacitor to be produced is formed from the layer sequence. Sides of the layer structure are provided with a conducting supporting structure. An opening is formed inside the layer structure, all the way down to the auxiliary layer and then the auxiliary layer and the layers made of the second material are removed. A free surface of the layers made of the first material and the supporting structure are provided with a capacitor dielectric onto which a counter electrode is applied.

Abstract: For manufacturing a capacitor, in particular for a dynamic memory cell arrangement, a trench is etched in a substrate. In the trench, a layer sequence is produced that contains, in alternating fashion, layers of doped silicon and germanium-containing layers. By anisotropic etching, the surface of the semiconductor substrate (12) is exposed in the region of the trench floor. The trenches are filled with a conductive support structure (20). The germanium-containing layers are removed selectively to the layers of doped silicon. The exposed surface of the layers of doped silicon (17) and of the support structure (20) are provided with a capacitor dielectric (22), onto which is applied a counter-electrode (23).

Abstract: A capacitor in a semiconductor configuration, especially a DRAM, includes an electrode structure having a plurality of spaced-apart elements being electrically connected with a connecting structure and all including p-conductive material with a doping >10.sup.10 cm.sup.-3. The elements of the electrode structure are either stacked or disposed side by side and may be cup-shaped. In a production process, a layer sequence of alternatingly one p.sup.- -doped and one p.sup.+ -doped layer is produced, which receives an opening through the use of anisotropic etching. At least in a peripheral region of the opening, a p.sup.+ -zone is created, which connects the layer sequence and forms the connecting structure. Next, the p.sup.- -doped layers are etched selectively to the p.sup.+ -doped layers, a capacitor dielectric is deposited, and a counterelectrode is produced.

Abstract: A circuit structure having at least one capacitor and a method for the manufacture thereof. The capacitor is constructed of a doped, single-crystal silicon substrate (1) that is provided with a plurality of hole openings (3) by electrochemical etching in a fluoride-containing, acidic electrolyte wherein the substrate is connected as an anode. The capacitor is further constructed of a dielectric layer (4) and of a conductive layer (5) as a cooperating electrode.

Abstract: A method used in manufacturing a cubically integrated circuit arrangement. A silicon wafer, wherein through pores are produced by electrochemical etching are insulated from the silicon wafer, and are provided with conductive fills, is secured as a carrier plate (24) to a substrate (21) that has components and that is integrated in a cubically integrated circuit arrangement. Terminal pads (25) that are electrically connected to conductive fills and that are arranged on the surface of the carrier plate (24) thereby meet contacts (23) to the components that are arranged at the surface of the substrate (21) adjoining the carrier plate (24) and that are firmly connected thereto.

Abstract: Through-holes are formed in a substrate wafer by electrochemical etching, so that a perforated, self-supporting layer of n-doped, monocrystalline silicon arises. An n-doped region and a p-doped region that form a pn-junction and that both adjoin a first principal face of the self-supporting layer are produced in the self-supporting layer. A contact to the n-doped region and a contact to the p-doped region are formed on the first principal face, so that the pn-junction can be interconnected as solar cell into which the light incidence can occur via a second principal face lying opposite the first.

Abstract: Rod-shaped or cylindrical structures in the nm range on a substrate of silicon are manufactured. A first cylinder of silicon is selectively epitaxially deposited in the hole of a mask layer of oxide, and the mask layer is removed. The silicon is then oxidized to form an oxide layer having such a thickness that a thinner, second cylinder of silicon having practically the same height as the first cylinder remains. In a last step, this oxide layer is removed, so that the second cylinder forms a freestanding silicon rod on the surface of the substrate.

Abstract: A multi-chip module has a carrier (21) of monocrystalline silicon whose surface is at least partially enlarged by anodic electro-chemical etching in a fluoride-containing acidic electrolyte. At least one capacitor (23) that has a dielectric layer and a conductive layer is arranged on the enlarged surface of the carrier (21), whereby the carrier (21) and the conductive layer act as capacitor electrodes.

Abstract: For manufacturing a component with porous silicon, two highly doped regions with a lightly doped region arranged between them are formed in a silicon wafer. The dopant concentrations are thereby set such that porous silicon arises in the lightly doped region in a subsequent anodic etching. Light-emitting diodes or light-controlled bipolar transistors can be manufactured in this way.

Abstract: A self-supporting layer of n-doped monocrystalline silicon is stripped from a substrate wafer of n-doped, monocrystalline silicon by electrochemical etching for manufacturing a solar cell. Holes are formed in the substrate wafer by electrochemical etching, particularly in a fluoride-containing, acidic electrolyte wherein the substrate wafer is connected as an anode. When a depth of the holes that essentially corresponds to the thickness of the self-supporting layer is reached, the process parameters of the etching are modified such that the self-supporting layer is stripped as a consequence of the holes growing together. The solar cell is manufactured from the self-supporting layer, and the method can be applied repeatedly on the same substrate wafer for stripping a plurality of self-supporting layers.

Abstract: For manufacturing an electrically conductive tip composed of a doped semiconductor material, a mask layer is produced on a substrate composed of the semiconductor material. This mask layer contains a material at least at its surface and directly on the substrate whereon the semiconductor material does not grow in a selective epitaxy. An opening wherein the surface of the substrate lies exposed is produced in the mask layer. The electrically conductive tip is produced by a selective epitaxy on the exposed surface of the substrate such that the layer growth in the direction parallel to the surface of the substrate is lower than in the direction perpendicular to the surface of the substrate.