Patents by Inventor Wolfgang Krautschneider
Wolfgang Krautschneider has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10881297Abstract: The invention proposes an In-situ Sensor (1) for being implanted within tissue of a mammal (P) comprising •an energy harvesting portion (RX), •a communication portion (TX), •a pressure sensor (SP) for measuring interstitial pressure of surrounding tissue when located within tissue, •a further sensor (SF), whereby the further sensor is selected from a group comprising pH sensor, lactate sensor, impedance sensor, radiation sensor, temperature sensor, sensor for bioelectrical potentials, •whereby said further sensor (SF), said pressure sensor (SP) as well as the communication portion (TX) are powered by the energy harvesting portion (RX), •whereby information indicative of the measurement provided by the pressure sensor (SP) and data indicative of the measurement provided by said further sensor (SF) is communicated via said communication portion (TX) towards an extracorporeal receiving entity (ECE), •whereby said communication portion (TX) and/or said pressure sensor (SP) and/or said further sensor (SF) are adapType: GrantFiled: June 16, 2017Date of Patent: January 5, 2021Assignees: TECHNISCHE UNIVERSITÄT HAMBURG, UNIVERSITÄTSKLINIKUM HAMBRUG-EPPENDORF (UKE)Inventors: Udo Schumacher, Wolfgang Krautschneider, Dietmar Schroder
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Publication number: 20190328230Abstract: The invention proposes an In-situ Sensor (1) for being implanted within tissue of a mammal (P) comprising •an energy harvesting portion (RX), •a communication portion (TX), •a pressure sensor (SP) for measuring interstitial pressure of surrounding tissue when located within tissue, •a further sensor (SF), whereby the further sensor is selected from a group comprising pH sensor, lactate sensor, impedance sensor, radiation sensor, temperature sensor, sensor for bioelectrical potentials, •whereby said further sensor (SF), said pressure sensor (SP) as well as the communication portion (TX) are powered by the energy harvesting portion (RX), •whereby information indicative of the measurement provided by the pressure sensor (SP) and data indicative of the measurement provided by said further sensor (SF) is communicated via said communication portion (TX) towards an extracorporeal receiving entity (ECE), •whereby said communication portion (TX) and/or said pressure sensor (SP) and/or said further sensor (SF) are adapType: ApplicationFiled: June 16, 2017Publication date: October 31, 2019Inventors: Udo SCHUMACHER, Wolfgang KRAUTSCHNEIDER, Dietmar SCHRODER
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Patent number: 7030434Abstract: A memory transistor and a selection transistor of an image sensor are connected in series and between a bit line (B5) and a reference line (R5). A gate electrode of the selection transistor is connected to a word line (W5), which extends crosswise in relation to the bit line (B5). A diode of the image sensor is switched between a gate electrode (G5) of the memory transistor and a first source/drain area (S/D5) of the memory transistor, which is connected to the selection transistor in such a way is polarized towards the first source/drain area (S/D5) of the memory transistor and in the reverse direction. A photodiode of the image sensor is switched between a voltage connection and either the gate electrode (G5) of the memory transistor or the first source/drain area (S/D5) of the memory transistor in such a way that it is polarized towards the voltage connection and in the reverse direction.Type: GrantFiled: September 28, 2000Date of Patent: April 18, 2006Assignee: Infineon Technologies AGInventors: Wolfgang Krautschneider, Heribert Geib, Franz Hofmann, Till Schlösser
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Patent number: 6593614Abstract: A patterned conductive layer and a structure via which a transistor can be driven, e.g. a word line, are disposed one above the other. A vertical conductive structure, e.g. a spacer, connects a first source/drain region of the transistor to the conductive layer, with which it forms a first capacitor electrode which has a large effective area in conjunction with a high packing density. A capacitor dielectric is disposed over the vertical conductive structure and the conductive layer, and a second capacitor electrode is disposed over the capacitor dielectric. The vertical conductive structure may be disposed on a first sidewall of the first source/drain region and a gate electrode of the transistor may be disposed on an adjoining second sidewall of the first source/drain region. The circuit configuration may form a DRAM cell configuration.Type: GrantFiled: November 20, 2000Date of Patent: July 15, 2003Assignee: Infineon-Technologies AGInventors: Franz Hofmann, Wolfgang Krautschneider
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Patent number: 6576948Abstract: An integrated circuit contains a planar first transistor and a diode. The diode is connected between a first source/drain region of the first transistor and a gate electrode of the first transistor such that a charge is impeded from discharging from the gate electrode to the first source/drain region. A diode layer that is part of the diode is disposed on a portion of the first source/drain region. A conductive structure that is an additional part of the diode is disposed above a portion of the gate electrode and is disposed on the diode layer. The diode can be configured as a tunnel diode. The diode layer can be produced by thermal oxidation. Only one mask is required for producing the diode. A capacitor can be disposed above the diode. The first capacitor electrode of the capacitor is connected to the conductive structure.Type: GrantFiled: June 4, 2001Date of Patent: June 10, 2003Assignee: Infineon Technologies AGInventors: Franz Hofmann, Wolfgang Krautschneider, Till Schlösser, Josef Willer
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Patent number: 6534820Abstract: An integrated dynamic memory cell having a small area of extent on a semiconductor substrate is described. The memory cell has a selection MOSFET with a gate connection area that is connected to a word line, a source connection doping area which is connected to a bit line, and a drain connection doping area. A memory MOSFET has a gate connection area which is connected via a thin dielectric layer to a connection doping region which connects a source connection doping area of the memory MOSFET to the drain connection doping area of the selection MOSFET. The memory MOSFET further has a drain connection doping area that is connected to a supply voltage. The selection and memory MOSFETs are disposed on opposite sidewalls of a trench, which is etched in the substrate, and the connection doping region forms a bottom of the trench.Type: GrantFiled: December 21, 2000Date of Patent: March 18, 2003Assignee: Infineon Technologies AGInventors: Franz Hofmann, Wolfgang Krautschneider, Till Schlösser
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Patent number: 6521935Abstract: A MOS transistor includes an upper source/drain region, a channel region, and a lower source/drain region that are stacked as layers one above the other and form a projection of a substrate. A gate dielectric adjoins a first lateral area of the projection. A gate electrode adjoins the gate dielectric. A conductive structure adjoins a second lateral area of the projection in the region of the channel region. The conductive structure adjoins the gate electrode.Type: GrantFiled: December 26, 2001Date of Patent: February 18, 2003Assignee: Infineon Technologies AGInventors: Wolfgang Krautschneider, Till Schlösser, Josef Willer
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Patent number: 6518628Abstract: An integrated CMOS circuit arrangement and a method of manufacturing same, which includes both a first MOS transistor and a second MOS transistor complementary thereto, wherein one of the MOS transistors is arranged at the floor of a trench and the other is arranged at the principal surface of a semiconductor substrate. The MOS transistors are arranged relative to one another such that a current flow through the MOS transistors respectively occurs substantially parallel to a sidewall of the trench that is arranged between the MOS transistors.Type: GrantFiled: November 15, 1999Date of Patent: February 11, 2003Assignee: Siemens AktiengesellschaftInventors: Wolfgang Krautschneider, Franz Hofmann, Lothar Risch
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Patent number: 6475866Abstract: A method for production of a memory cell arrangement which includes vertical MOS transistors as memory cells, wherein the information is stored utilizing at least three different threshold voltage values of the transistors by multi-level programming. One threshold voltage value is realised by the thickness of the gate dielectric in the sense of a thick oxide transistor and the other threshold voltage values are realised by different channel dopings. The arrangement can be produced with as area requirement for each memory cell of 2 F2 (F: minimum structure size).Type: GrantFiled: January 31, 2001Date of Patent: November 5, 2002Assignee: Siemens AktiengesellschaftInventors: Franz Hofmann, Wolfgang Krautschneider, Josef Willer
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Patent number: 6445046Abstract: A number of memory cell lines insulated from one another and that respectively comprise a first doped region and a second doped region between which a gate dielectric, which contains a material with charge carrier traps and a number of gate electrodes. The spacing of neighboring gate electrodes is smaller than the dimensions of the gate electrodes. The information is stored by introduction of charge carriers into the gate dielectric. The gate electrodes are preferably manufactured with the assistance of a spacer technique.Type: GrantFiled: June 15, 1999Date of Patent: September 3, 2002Assignee: Siemens AktiengesellschaftInventors: Franz Hofmann, Josef Willer, Hans Reisinger, Paul Werner von Basse, Wolfgang Krautschneider
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Patent number: 6442065Abstract: Each memory cell of a cell configuration includes at least one memory transistor. To write first or second information on the memory cell, a gate electrode of the memory transistor is charged such that a first voltage or a second voltage is applied in the memory transistor. A reading voltage is applied in a second source/drain area of the memory transistor to read first information and second information respectively. The first voltage is applied between the second voltage and the reading voltage. The reading voltage is applied between the first voltage less a threshold voltage of the memory transistor and the second voltage less the threshold voltage of the memory transistor.Type: GrantFiled: August 22, 2001Date of Patent: August 27, 2002Assignee: Infineon Technologies AGInventors: Franz Hofmann, Wolfgang Krautschneider, Till Schlösser, Josef Willer
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Patent number: 6438022Abstract: The memory cells of a memory cell configuration each have a selection transistor, a memory transistor and a ferroelectric capacitor. The selection transistor and the memory transistor are connected in series. The ferroelectric capacitor is connected between a control electrode of the memory transistor and a first terminal of the selection transistor.Type: GrantFiled: May 10, 2001Date of Patent: August 20, 2002Assignee: Infineon Technologies AGInventors: Till Schlösser, Wolfgang Krautschneider, Franz Hofmann, Thomas-Peter Haneder
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Publication number: 20020096699Abstract: A MOS transistor includes an upper source/drain region, a channel region, and a lower source/drain region that are stacked as layers one above the other and form a projection of a substrate. A gate dielectric adjoins a first lateral area of the projection. A gate electrode adjoins the gate dielectric. A conductive structure adjoins a second lateral area of the projection in the region of the channel region. The conductive structure adjoins the gate electrode.Type: ApplicationFiled: December 26, 2001Publication date: July 25, 2002Inventors: Wolfgang Krautschneider, Till Schlosser, Josef Willer
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Publication number: 20020075723Abstract: Each memory cell of a cell configuration includes at least one memory transistor. To write first or second information on the memory cell, a gate electrode of the memory transistor is charged such that a first voltage or a second voltage is applied in the memory transistor. A reading voltage is applied in a second source/drain area of the memory transistor to read first information and second information respectively. The first voltage is applied between the second voltage and the reading voltage. The reading voltage is applied between the first voltage less a threshold voltage of the memory transistor and the second voltage less the threshold voltage of the memory transistor.Type: ApplicationFiled: August 22, 2001Publication date: June 20, 2002Inventors: Franz Hofmann, Wolfgang Krautschneider, Till Schlosser, Josef Willer
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Patent number: 6399433Abstract: A method for producing a storage cell includes forming a polycrystalline silicon layer on a semiconductor body having at least one selection transistor disposed in a first plane. An interspace is formed between two adjacent structures of the layer and one of the adjacent structures of the layer is placed on a surface of a first silicon plug. A cell plate electrode is formed in the interspace and a trench is formed in the layer. The trench reaches as far as the first plug surface and is filled with an insulating layer. The-layer is removed. A storage capacitor having a high-epsilon or ferroelectric dielectric and a storage node electrode is formed. The capacitor is disposed in a second plane in and above the body. The insulating layer is replaced with silicon to form a second silicon plug directly connected to the first plug. The second plug is electrically connected to the storage node electrode, and the first plane is electrically connected to the second plane through the first and second plugs.Type: GrantFiled: January 31, 2001Date of Patent: June 4, 2002Assignee: Infineon Technologies AGInventors: Franz Hofmann, Wolfgang Krautschneider, Till Schlösser, Josef Willer
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Publication number: 20010054727Abstract: An integrated circuit contains a planar first transistor and a diode. The diode is connected between a first source/drain region of the first transistor and a gate electrode of the first transistor such that a charge is impeded from discharging from the gate electrode to the first source/drain region. A diode layer that is part of the diode is disposed on a portion of the first source/drain region. A conductive structure that is an additional part of the diode is disposed above a portion of the gate electrode and is disposed on the diode layer. The diode can be configured as a tunnel diode. The diode layer can be produced by thermal oxidation. Only one mask is required for producing the diode. A capacitor can be disposed above the diode. The first capacitor electrode of the capacitor is connected to the conductive structure.Type: ApplicationFiled: June 4, 2001Publication date: December 27, 2001Inventors: Franz Hofmann, Wolfgang Krautschneider, Till Schlosser, Josef Willer
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Publication number: 20010036101Abstract: The memory cells of a memory cell configuration each have a selection transistor, a memory transistor and a ferroelectric capacitor. The selection transistor and the memory transistor are connected in series. The ferroelectric capacitor is connected between a control electrode of the memory transistor and a first terminal of the selection transistor.Type: ApplicationFiled: May 10, 2001Publication date: November 1, 2001Inventors: Till Schlosser, Wolfgang Krautschneider, Franz Hofmann, Thomas-Peter Haneder
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Publication number: 20010031529Abstract: A method for producing a storage cell includes forming a polycrystalline silicon layer on a semiconductor body having at least one selection transistor disposed in a first plane. An interspace is formed between two adjacent structures of the layer and one of the adjacent structures of the layer is placed on a surface of a first silicon plug. A cell plate electrode is formed in the interspace and a trench is formed in the layer. The trench reaches as far as the first plug surface and is filled with an insulating layer. The layer is removed. A storage capacitor having a high-epsilon or ferroelectric dielectric and a storage node electrode is formed. The capacitor is disposed in a second plane in and above the body. The insulating layer is replaced with silicon to form a second silicon plug directly connected to the first plug. The second plug is electrically connected to the storage node electrode, and the first plane is electrically connected to the second plane through the first and second plugs.Type: ApplicationFiled: January 31, 2001Publication date: October 18, 2001Inventors: Franz Hofmann, Wolfgang Krautschneider, Till Schlosser, Josef Willer
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Publication number: 20010017795Abstract: An integrated dynamic memory cell having a small area of extent on a semiconductor substrate is described. The memory cell has a selection MOSFET with a gate connection area that is connected to a word line, a source connection doping area which is connected to a bit line, and a drain connection doping area. A memory MOSFET has a gate connection area which is connected via a thin dielectric layer to a connection doping region which connects a source connection doping area of the memory MOSFET to the drain connection doping area of the selection MOSFET. The memory MOSFET further has a drain connection doping area that is connected to a supply voltage. The selection and memory MOSFETs are disposed on opposite sidewalls of a trench, which is etched in the substrate, and the connection doping region forms a bottom of the trench.Type: ApplicationFiled: December 21, 2000Publication date: August 30, 2001Inventors: Franz Hofmann, Wolfgang Krautschneider, Till Schlosser
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Patent number: 6274431Abstract: An integrated circuit arrangement contains an MOS transistor surrounded by an insulation structure, the source and drain thereof being arranged laterally and in different depths. A channel thereof proceeds essentially perpendicular to the surface of the circuit arrangement. Since the channel length is determined by etching or by growing a layer, channel lengths as short as less than 50 nm can be realized. For the manufacture, most of the masks of the traditional circuit arrangements in which planar transistors are integrated are employed, this significantly facilitating incorporation into the semiconductor manufacture.Type: GrantFiled: April 28, 1999Date of Patent: August 14, 2001Assignee: Siemens AktiengesellschaftInventors: Lothar Risch, Wolfgang Roesner, Thomas Aeugle, Wolfgang Krautschneider