Patents by Inventor Wolfgang Krautschneider

Wolfgang Krautschneider has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7030434
    Abstract: A memory transistor and a selection transistor of an image sensor are connected in series and between a bit line (B5) and a reference line (R5). A gate electrode of the selection transistor is connected to a word line (W5), which extends crosswise in relation to the bit line (B5). A diode of the image sensor is switched between a gate electrode (G5) of the memory transistor and a first source/drain area (S/D5) of the memory transistor, which is connected to the selection transistor in such a way is polarized towards the first source/drain area (S/D5) of the memory transistor and in the reverse direction. A photodiode of the image sensor is switched between a voltage connection and either the gate electrode (G5) of the memory transistor or the first source/drain area (S/D5) of the memory transistor in such a way that it is polarized towards the voltage connection and in the reverse direction.
    Type: Grant
    Filed: September 28, 2000
    Date of Patent: April 18, 2006
    Assignee: Infineon Technologies AG
    Inventors: Wolfgang Krautschneider, Heribert Geib, Franz Hofmann, Till Schlösser
  • Patent number: 6593614
    Abstract: A patterned conductive layer and a structure via which a transistor can be driven, e.g. a word line, are disposed one above the other. A vertical conductive structure, e.g. a spacer, connects a first source/drain region of the transistor to the conductive layer, with which it forms a first capacitor electrode which has a large effective area in conjunction with a high packing density. A capacitor dielectric is disposed over the vertical conductive structure and the conductive layer, and a second capacitor electrode is disposed over the capacitor dielectric. The vertical conductive structure may be disposed on a first sidewall of the first source/drain region and a gate electrode of the transistor may be disposed on an adjoining second sidewall of the first source/drain region. The circuit configuration may form a DRAM cell configuration.
    Type: Grant
    Filed: November 20, 2000
    Date of Patent: July 15, 2003
    Assignee: Infineon-Technologies AG
    Inventors: Franz Hofmann, Wolfgang Krautschneider
  • Patent number: 6576948
    Abstract: An integrated circuit contains a planar first transistor and a diode. The diode is connected between a first source/drain region of the first transistor and a gate electrode of the first transistor such that a charge is impeded from discharging from the gate electrode to the first source/drain region. A diode layer that is part of the diode is disposed on a portion of the first source/drain region. A conductive structure that is an additional part of the diode is disposed above a portion of the gate electrode and is disposed on the diode layer. The diode can be configured as a tunnel diode. The diode layer can be produced by thermal oxidation. Only one mask is required for producing the diode. A capacitor can be disposed above the diode. The first capacitor electrode of the capacitor is connected to the conductive structure.
    Type: Grant
    Filed: June 4, 2001
    Date of Patent: June 10, 2003
    Assignee: Infineon Technologies AG
    Inventors: Franz Hofmann, Wolfgang Krautschneider, Till Schlösser, Josef Willer
  • Patent number: 6534820
    Abstract: An integrated dynamic memory cell having a small area of extent on a semiconductor substrate is described. The memory cell has a selection MOSFET with a gate connection area that is connected to a word line, a source connection doping area which is connected to a bit line, and a drain connection doping area. A memory MOSFET has a gate connection area which is connected via a thin dielectric layer to a connection doping region which connects a source connection doping area of the memory MOSFET to the drain connection doping area of the selection MOSFET. The memory MOSFET further has a drain connection doping area that is connected to a supply voltage. The selection and memory MOSFETs are disposed on opposite sidewalls of a trench, which is etched in the substrate, and the connection doping region forms a bottom of the trench.
    Type: Grant
    Filed: December 21, 2000
    Date of Patent: March 18, 2003
    Assignee: Infineon Technologies AG
    Inventors: Franz Hofmann, Wolfgang Krautschneider, Till Schlösser
  • Patent number: 6521935
    Abstract: A MOS transistor includes an upper source/drain region, a channel region, and a lower source/drain region that are stacked as layers one above the other and form a projection of a substrate. A gate dielectric adjoins a first lateral area of the projection. A gate electrode adjoins the gate dielectric. A conductive structure adjoins a second lateral area of the projection in the region of the channel region. The conductive structure adjoins the gate electrode.
    Type: Grant
    Filed: December 26, 2001
    Date of Patent: February 18, 2003
    Assignee: Infineon Technologies AG
    Inventors: Wolfgang Krautschneider, Till Schlösser, Josef Willer
  • Patent number: 6518628
    Abstract: An integrated CMOS circuit arrangement and a method of manufacturing same, which includes both a first MOS transistor and a second MOS transistor complementary thereto, wherein one of the MOS transistors is arranged at the floor of a trench and the other is arranged at the principal surface of a semiconductor substrate. The MOS transistors are arranged relative to one another such that a current flow through the MOS transistors respectively occurs substantially parallel to a sidewall of the trench that is arranged between the MOS transistors.
    Type: Grant
    Filed: November 15, 1999
    Date of Patent: February 11, 2003
    Assignee: Siemens Aktiengesellschaft
    Inventors: Wolfgang Krautschneider, Franz Hofmann, Lothar Risch
  • Patent number: 6475866
    Abstract: A method for production of a memory cell arrangement which includes vertical MOS transistors as memory cells, wherein the information is stored utilizing at least three different threshold voltage values of the transistors by multi-level programming. One threshold voltage value is realised by the thickness of the gate dielectric in the sense of a thick oxide transistor and the other threshold voltage values are realised by different channel dopings. The arrangement can be produced with as area requirement for each memory cell of 2 F2 (F: minimum structure size).
    Type: Grant
    Filed: January 31, 2001
    Date of Patent: November 5, 2002
    Assignee: Siemens Aktiengesellschaft
    Inventors: Franz Hofmann, Wolfgang Krautschneider, Josef Willer
  • Patent number: 6445046
    Abstract: A number of memory cell lines insulated from one another and that respectively comprise a first doped region and a second doped region between which a gate dielectric, which contains a material with charge carrier traps and a number of gate electrodes. The spacing of neighboring gate electrodes is smaller than the dimensions of the gate electrodes. The information is stored by introduction of charge carriers into the gate dielectric. The gate electrodes are preferably manufactured with the assistance of a spacer technique.
    Type: Grant
    Filed: June 15, 1999
    Date of Patent: September 3, 2002
    Assignee: Siemens Aktiengesellschaft
    Inventors: Franz Hofmann, Josef Willer, Hans Reisinger, Paul Werner von Basse, Wolfgang Krautschneider
  • Patent number: 6442065
    Abstract: Each memory cell of a cell configuration includes at least one memory transistor. To write first or second information on the memory cell, a gate electrode of the memory transistor is charged such that a first voltage or a second voltage is applied in the memory transistor. A reading voltage is applied in a second source/drain area of the memory transistor to read first information and second information respectively. The first voltage is applied between the second voltage and the reading voltage. The reading voltage is applied between the first voltage less a threshold voltage of the memory transistor and the second voltage less the threshold voltage of the memory transistor.
    Type: Grant
    Filed: August 22, 2001
    Date of Patent: August 27, 2002
    Assignee: Infineon Technologies AG
    Inventors: Franz Hofmann, Wolfgang Krautschneider, Till Schlösser, Josef Willer
  • Patent number: 6438022
    Abstract: The memory cells of a memory cell configuration each have a selection transistor, a memory transistor and a ferroelectric capacitor. The selection transistor and the memory transistor are connected in series. The ferroelectric capacitor is connected between a control electrode of the memory transistor and a first terminal of the selection transistor.
    Type: Grant
    Filed: May 10, 2001
    Date of Patent: August 20, 2002
    Assignee: Infineon Technologies AG
    Inventors: Till Schlösser, Wolfgang Krautschneider, Franz Hofmann, Thomas-Peter Haneder
  • Publication number: 20020096699
    Abstract: A MOS transistor includes an upper source/drain region, a channel region, and a lower source/drain region that are stacked as layers one above the other and form a projection of a substrate. A gate dielectric adjoins a first lateral area of the projection. A gate electrode adjoins the gate dielectric. A conductive structure adjoins a second lateral area of the projection in the region of the channel region. The conductive structure adjoins the gate electrode.
    Type: Application
    Filed: December 26, 2001
    Publication date: July 25, 2002
    Inventors: Wolfgang Krautschneider, Till Schlosser, Josef Willer
  • Publication number: 20020075723
    Abstract: Each memory cell of a cell configuration includes at least one memory transistor. To write first or second information on the memory cell, a gate electrode of the memory transistor is charged such that a first voltage or a second voltage is applied in the memory transistor. A reading voltage is applied in a second source/drain area of the memory transistor to read first information and second information respectively. The first voltage is applied between the second voltage and the reading voltage. The reading voltage is applied between the first voltage less a threshold voltage of the memory transistor and the second voltage less the threshold voltage of the memory transistor.
    Type: Application
    Filed: August 22, 2001
    Publication date: June 20, 2002
    Inventors: Franz Hofmann, Wolfgang Krautschneider, Till Schlosser, Josef Willer
  • Patent number: 6399433
    Abstract: A method for producing a storage cell includes forming a polycrystalline silicon layer on a semiconductor body having at least one selection transistor disposed in a first plane. An interspace is formed between two adjacent structures of the layer and one of the adjacent structures of the layer is placed on a surface of a first silicon plug. A cell plate electrode is formed in the interspace and a trench is formed in the layer. The trench reaches as far as the first plug surface and is filled with an insulating layer. The-layer is removed. A storage capacitor having a high-epsilon or ferroelectric dielectric and a storage node electrode is formed. The capacitor is disposed in a second plane in and above the body. The insulating layer is replaced with silicon to form a second silicon plug directly connected to the first plug. The second plug is electrically connected to the storage node electrode, and the first plane is electrically connected to the second plane through the first and second plugs.
    Type: Grant
    Filed: January 31, 2001
    Date of Patent: June 4, 2002
    Assignee: Infineon Technologies AG
    Inventors: Franz Hofmann, Wolfgang Krautschneider, Till Schlösser, Josef Willer
  • Publication number: 20010054727
    Abstract: An integrated circuit contains a planar first transistor and a diode. The diode is connected between a first source/drain region of the first transistor and a gate electrode of the first transistor such that a charge is impeded from discharging from the gate electrode to the first source/drain region. A diode layer that is part of the diode is disposed on a portion of the first source/drain region. A conductive structure that is an additional part of the diode is disposed above a portion of the gate electrode and is disposed on the diode layer. The diode can be configured as a tunnel diode. The diode layer can be produced by thermal oxidation. Only one mask is required for producing the diode. A capacitor can be disposed above the diode. The first capacitor electrode of the capacitor is connected to the conductive structure.
    Type: Application
    Filed: June 4, 2001
    Publication date: December 27, 2001
    Inventors: Franz Hofmann, Wolfgang Krautschneider, Till Schlosser, Josef Willer
  • Publication number: 20010036101
    Abstract: The memory cells of a memory cell configuration each have a selection transistor, a memory transistor and a ferroelectric capacitor. The selection transistor and the memory transistor are connected in series. The ferroelectric capacitor is connected between a control electrode of the memory transistor and a first terminal of the selection transistor.
    Type: Application
    Filed: May 10, 2001
    Publication date: November 1, 2001
    Inventors: Till Schlosser, Wolfgang Krautschneider, Franz Hofmann, Thomas-Peter Haneder
  • Publication number: 20010031529
    Abstract: A method for producing a storage cell includes forming a polycrystalline silicon layer on a semiconductor body having at least one selection transistor disposed in a first plane. An interspace is formed between two adjacent structures of the layer and one of the adjacent structures of the layer is placed on a surface of a first silicon plug. A cell plate electrode is formed in the interspace and a trench is formed in the layer. The trench reaches as far as the first plug surface and is filled with an insulating layer. The layer is removed. A storage capacitor having a high-epsilon or ferroelectric dielectric and a storage node electrode is formed. The capacitor is disposed in a second plane in and above the body. The insulating layer is replaced with silicon to form a second silicon plug directly connected to the first plug. The second plug is electrically connected to the storage node electrode, and the first plane is electrically connected to the second plane through the first and second plugs.
    Type: Application
    Filed: January 31, 2001
    Publication date: October 18, 2001
    Inventors: Franz Hofmann, Wolfgang Krautschneider, Till Schlosser, Josef Willer
  • Publication number: 20010017795
    Abstract: An integrated dynamic memory cell having a small area of extent on a semiconductor substrate is described. The memory cell has a selection MOSFET with a gate connection area that is connected to a word line, a source connection doping area which is connected to a bit line, and a drain connection doping area. A memory MOSFET has a gate connection area which is connected via a thin dielectric layer to a connection doping region which connects a source connection doping area of the memory MOSFET to the drain connection doping area of the selection MOSFET. The memory MOSFET further has a drain connection doping area that is connected to a supply voltage. The selection and memory MOSFETs are disposed on opposite sidewalls of a trench, which is etched in the substrate, and the connection doping region forms a bottom of the trench.
    Type: Application
    Filed: December 21, 2000
    Publication date: August 30, 2001
    Inventors: Franz Hofmann, Wolfgang Krautschneider, Till Schlosser
  • Patent number: 6274453
    Abstract: A memory cell configuration with many ferroelectric or dynamic memory cells provided in a semiconductor substrate. Alternating trenches and lands extend parallel in a longitudinal direction of a main face of the semiconductor substrate. A channel stop layer is buried in the lands and divides the semiconductor substrate into a lower region that includes the trench bottoms and an upper region that includes the land ridges. First planar selection transistors with intervening trench channel stop regions are disposed along the trench bottoms. Second planar selection transistors with intervening land channel stop regions are disposed along the land ridges. The first and second selection transistors have respective source, gate, channel and drain regions, which are offset longitudinally from one another such that source and drain regions of the first and second selection transistors alternate in the transverse direction in the main face of the semiconductor substrate.
    Type: Grant
    Filed: September 24, 1999
    Date of Patent: August 14, 2001
    Assignee: Siemens Aktiengesellschaft
    Inventors: Till Schlösser, Franz Hofmann, Wolfgang Krautschneider
  • Patent number: 6274431
    Abstract: An integrated circuit arrangement contains an MOS transistor surrounded by an insulation structure, the source and drain thereof being arranged laterally and in different depths. A channel thereof proceeds essentially perpendicular to the surface of the circuit arrangement. Since the channel length is determined by etching or by growing a layer, channel lengths as short as less than 50 nm can be realized. For the manufacture, most of the masks of the traditional circuit arrangements in which planar transistors are integrated are employed, this significantly facilitating incorporation into the semiconductor manufacture.
    Type: Grant
    Filed: April 28, 1999
    Date of Patent: August 14, 2001
    Assignee: Siemens Aktiengesellschaft
    Inventors: Lothar Risch, Wolfgang Roesner, Thomas Aeugle, Wolfgang Krautschneider
  • Patent number: 6265748
    Abstract: A memory cell arrangement, and method for producing same, which includes vertical MOS transistors as memory cells wherein the information is stored by means of at least three different threshold voltage values of the transistors by multi-level programming. One threshold voltage value is obtained by the thickness of the gate dielectric in the sense of a thick oxide transistor and the other threshold voltage values are obtained by different channel dopings. The arrangement can be produced with an area requirement for each memory cell of 2 F2 (F: minimum structure size).
    Type: Grant
    Filed: November 2, 1998
    Date of Patent: July 24, 2001
    Assignee: Siemens Aktiengesellschaft
    Inventors: Franz Hofmann, Wolfgang Krautschneider, Josef Willer