Abstract: A memory cell configuration with many ferroelectric or dynamic memory cells provided in a semiconductor substrate. Alternating trenches and lands extend parallel in a longitudinal direction of a main face of the semiconductor substrate. A channel stop layer is buried in the lands and divides the semiconductor substrate into a lower region that includes the trench bottoms and an upper region that includes the land ridges. First planar selection transistors with intervening trench channel stop regions are disposed along the trench bottoms. Second planar selection transistors with intervening land channel stop regions are disposed along the land ridges. The first and second selection transistors have respective source, gate, channel and drain regions, which are offset longitudinally from one another such that source and drain regions of the first and second selection transistors alternate in the transverse direction in the main face of the semiconductor substrate.

Abstract: A memory cell arrangement, and method for producing same, which includes vertical MOS transistors as memory cells wherein the information is stored by means of at least three different threshold voltage values of the transistors by multi-level programming. One threshold voltage value is obtained by the thickness of the gate dielectric in the sense of a thick oxide transistor and the other threshold voltage values are obtained by different channel dopings. The arrangement can be produced with an area requirement for each memory cell of 2 F2 (F: minimum structure size).

Abstract: In a memory cell arrangement which comprises vertical MOS transistors as memory cells, the information is stored by means of at least three different threshold voltage values of the transistors by multi-level programming. One threshold voltage value is realised by the thickness of the gate dielectric in the sense of a thick oxide transistor and the other threshold voltage values are realised by different channel dopings. The arrangement can be produced with an area requirement for each memory cell of 2 F2 (F: minimum structure size).

Abstract: A memory cell configuration contains a multiplicity of memory cells in a semiconductor substrate. Each of the memory cells has a selection transistor connected between a bit line and a storage element. The memory cells can each be driven via a first word line and a second word line, the first word line and the second word line crossing one another. The memory cell configuration is, in particular, a DRAM configuration.

Abstract: An electrically programmable memory cell array is formed of memory cells, which include a vertical MOS transistor. The MOS transistor has a gate dielectric of a material with charge carrier traps. The memory cells are disposed along opposite edges of striplike, parallel insulation trenches. The width and spacing of the insulation trenches are preferably identical. The space required per memory cell of the memory cell array is 2F2, where F is the minimum structural size in the technology employed. The memory cells are programmed by selectively injecting electrons into the gate dielectric.

Abstract: A memory cell contains at least one transistor and one capacitor connected to an upper bit line. The capacitor contains a first capacitor electrode arranged above the transistor, and is connected to the transistor. The upper bit line can be created in self-adjusted fashion on the basis of trenches which are of different widths, which extend transversely to one another, and which are arranged between the first capacitor electrodes. At least a part of each first capacitor electrode can be created from a layer which is structured by the trenches. Trenches can be narrowed by spacers.

Abstract: A memory cell configuration includes first memory cells with planar MOS transistors and second memory cells with vertical MOS transistors. The planar MOS transistors are disposed on the bottom of and on the crown of parallel, strip-like trenches. The vertical MOS transistors are disposed on the side walls of the trenches. The memory cell configuration can be produced with a mean area requirement for each memory cell of 1 F2, where F is the minimum structure size.

Abstract: In a memory cell arrangement which has vertical MOS transistors as memory cells, the information is stored by different threshold voltages of the transistors. For this purpose, dopant regions are formed for an information state by angled implantation or outdiffusion in the upper region of the channel region. The lower region of the channel region is in this case covered by an etching residue (9′) which is formed by masked spacer etching. The arrangement can be produced with an area requirement for each memory cell of 2 F2 (F: minimum structure size).

Abstract: For the manufacture of a memory cell arrangement with first memory cells that comprise a vertical MOS transistor and with second memory cells that do not comprise an MOS transistor, whereby the memory cells are arranged along opposite edges of strip-type trenches, memory cells that are adjacent along the trenches (5) are manufactured successively. The spacing of adjacent memory cells is determined in particular by means of a spacer technology. By this means, a space requirement per memory cell of 1F.sup.2 can be realized, whereby F is the minimum structural size of the respective technology.

Abstract: A memory cell contains at least one transistor and one capacitor connected to an upper bit line. The capacitor contains a first capacitor electrode arranged above the transistor, and is connected to the transistor. The upper bit line can be created in self-adjusted fashion on the basis of trenches which are of different widths, which extend transversely to one another, and which are arranged between the first capacitor electrodes. At least a part of each first capacitor electrode can be created from a layer which is structured by the trenches. Trenches can be narrowed by spacers.

Abstract: Parallel lines, for example bit lines in a memory cell configuration formed of doped regions in a semiconductor substrate, are driven by electrically connecting a number of the lines to one another and to a common node. A number of selection lines extend transversely to the lines. MOS transistors are arranged at the points of intersection and are connected in series along one of the lines. The gate electrode of the MOS transistors is formed by the corresponding selection line. At least one MOS transistor in each of the parallel lines has a higher threshold voltage than the others.

Abstract: An integrated circuit arrangement contains an MOS transistor surrounded by an insulation structure, the source and drain thereof being arranged laterally and in different depths. A channel thereof proceeds essentially perpendicular to the surface of the circuit arrangement. Since the channel length is determined by etching or by growing a layer, channel lengths as short as less than 50 nm can be realized. For the manufacture, most of the masks of the traditional circuit arrangements in which planar transistors are integrated are employed, this significantly facilitating incorporation into the semiconductor manufacture.

Abstract: A read-only memory cell arrangement having planar MOS transistors which are arranged in parallel rows. Neighboring rows run alternately on the bottom of longitudinal trenches and run between neighboring longitudinal trenches. Bit lines run transversely and word lines run parallel to the longitudinal trenches. The memory cell arrangement can be produced with an area per memory cell of 2F.sup.2 (F-minimum structure size).

Abstract: A DRAM cell arrangement having dynamic, self-amplifying memory cells, and method for manufacturing same, wherein each memory cell includes a selection transistor, a memory transistor and a diode structure. The selection transistor and the memory transistor are each fashioned as vertical MOS transistors and are arranged one over the other such that they are connected to one another via a common source/drain region. A source/drain region of the memory transistor is connected to a supply voltage line, a source/drain region of the selection transistor is connected to a bitline, and the gate electrode of the selection transistor is connected to a wordline. A diode structure is connected between the common source/drain region and the gate electrode of the memory transistor.

Abstract: For the operation of a memory cell arrangement with MOS transistors as memory cells that comprise a dielectric triple layer (5) with a first silicon oxide layer (51), a silicon nitride layer (52) and a second silicon oxide layer (53) as gate dielectric, whereby the silicon oxide layers are respectively at least 3 nm thick, a first cutoff voltage value is allocated to a first logical value and a second cutoff voltage value of the MOS transistor is allocated to a second logical value for storing digital data. The information stored in the memory cell can be modified by applying corresponding voltage levels, although a complete removal of charge stored in the silicon nitride layer is not possible because of the thickness of the silicon oxide layers. What is exploited when modifying the cutoff voltage is that the electrical field in the dielectric triple layer is distorted by charge stored in the silicon nitride layer.

Abstract: An electrically writable and erasable read-only memory cell arrangement fabricated in a semiconductor substrate, preferably of monocrystalline silicon, or in a silicon layer of an SOI substrate. A cell array with memory cells is provided on a main surface of the semiconductor substrate. Each memory cell comprises an MOS transistor, vertical to the main surface and comprising, in addition to the source/drain region and a channel region arranged in-between, a first dielectric, a floating gate, a second dielectric and a control gate. A plurality of essentially parallel strip-shaped trenches are provided in the cell array. The vertical MOS transistors are arranged on the flanks of the trenches. The memory cells are in each case arranged on opposite flanks of the trenches.

Abstract: The memory cell has transistors that are arranged three-dimensionally. Vertical MOS transistors are arranged on the sidewalls of semiconductor webs, and a plurality of transistors are arranged one above the other on each sidewall. The transistors that are arranged one above the other on a sidewall are connected in series.

Abstract: An integrated circuit arrangement having at least two components has in a substrate, an insulation structure (4', 5) between the components which covers at least one side of a trench (3) and is thicker at the bottom of the trench than at the neck of the trench. The components are in this case arranged in different planes on the substrate surface and on the trench bottom. The insulation structure effects vertical insulation between the components.

Abstract: A memory cell containing at least three vertical transistors. A first transistor and a second transistor, or a third transistor are arranged over each other with reference to a y-axis proceeding perpendicularly to a surface of a substrate. The second transistor and the third transistor can be arranged at opposite sides of a semiconductor structure, while the first transistor is arranged at both sides. Source/drain regions of the transistors can overlap.

Abstract: A read-only-memory cell arrangement comprises memory cells, each having a vertical MOS transistor, in a substrate (21) made of semiconductor material, the various logic values (zero, one) being implemented by gate dielectrics (27, 28) of different thickness. The memory cell arrangement can preferably be produced in a silicon substrate, with a small number of process steps and a high packing density. The memory cell arrangement and a drive circuit for read-out can in this case be produced in an integrated manner.