Patents by Inventor Wolfgang Lehnert

Wolfgang Lehnert has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140070232
    Abstract: A composite wafer including a carrier substrate having a graphite core and a monocrystalline semiconductor substrate or layer attached to the carrier substrate and a corresponding method for manufacturing such a composite wafer is provided.
    Type: Application
    Filed: February 26, 2013
    Publication date: March 13, 2014
    Inventors: Rudolf Berger, Hermann Gruber, Wolfgang Lehnert, Guenther Ruhl, Raimund Foerg, Anton Mauder, Hans-Joachim Schulze
  • Patent number: 8404562
    Abstract: According to an embodiment, a composite wafer includes a carrier substrate having a graphite core and a monocrystalline semiconductor layer attached to the carrier substrate.
    Type: Grant
    Filed: September 30, 2010
    Date of Patent: March 26, 2013
    Assignee: Infineon Technologies AG
    Inventors: Rudolf Berger, Hermann Gruber, Wolfgang Lehnert, Guenther Ruhl, Raimund Foerg, Anton Mauder, Hans-Joachim Schulze
  • Patent number: 8318575
    Abstract: In one embodiment a method of forming a compressive polycrystalline semiconductive material layer is disclosed. The method comprises forming a polycrystalline semiconductive seed layer over a substrate and forming a silicon layer by depositing silicon directly on the polycrystalline silicon seed layer under amorphous process conditions at a temperature below 600 C.
    Type: Grant
    Filed: February 7, 2011
    Date of Patent: November 27, 2012
    Assignee: Infineon Technologies AG
    Inventors: Wolfgang Lehnert, Stefan Pompl, Markus Meyer
  • Publication number: 20120289023
    Abstract: A method for producing a semiconductor device having a sidewall insulation includes providing a semiconductor body having a first side and a second side lying opposite the first side. At least one first trench is at least partly filled with insulation material proceeding from the first side in the direction toward the second side into the semiconductor body. The at least one first trench is produced between a first semiconductor body region for a first semiconductor device and a second semiconductor body region for a second semiconductor device. An isolating trench extends from the first side of the semiconductor body in the direction toward the second side of the semiconductor body between the first and second semiconductor body regions in such a way that at least part of the insulation material of the first trench adjoins at least a sidewall of the isolating trench. The second side of the semiconductor body is partly removed as far as the isolating trench.
    Type: Application
    Filed: February 3, 2012
    Publication date: November 15, 2012
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Carsten Ahrens, Rudolf Berger, Manfred Frank, Uwe Hoeckele, Bernhard Knott, Ulrich Krumbein, Wolfgang Lehnert, Berthold Schuderer, Juergen Wagner, Stefan Willkofer
  • Publication number: 20120286355
    Abstract: A power semiconductor device has a semiconductor body which includes an active area and a peripheral area which both define a horizontal main surface of the semiconductor body. The semiconductor body further includes an n-type semiconductor layer, a pn junction and at least one trench. The n-type semiconductor layer is embedded in the semiconductor body and extends to the main surface in the peripheral area. The pn junction is arranged between the n-type semiconductor layer and the main surface in the active area. The at least one trench extends in the peripheral area from the main surface into the n-type semiconductor layer and includes a dielectric layer with fixed negative charges. In the vertical direction, the dielectric layer is arranged both below and above the pn junction. The dielectric layer with fixed negative charges typically has a negative net charge. Further, a method for forming a semiconductor device is provided.
    Type: Application
    Filed: July 6, 2012
    Publication date: November 15, 2012
    Applicant: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventors: Anton Mauder, Franz Hirler, Wolfgang Lehnert, Rudolf Berger, Klemens Pruegl, Hans-Joachim Schulze, Helmut Strack
  • Publication number: 20120202327
    Abstract: In one embodiment a method of forming a compressive polycrystalline semiconductive material layer is disclosed. The method comprises forming a polycrystalline semiconductive seed layer over a substrate and forming a silicon layer by depositing silicon directly on the polycrystalline silicon seed layer under amorphous process conditions at a temperature below 600 C.
    Type: Application
    Filed: February 7, 2011
    Publication date: August 9, 2012
    Inventors: Wolfgang Lehnert, Stefan Pompl, Markus Meyer
  • Publication number: 20120181656
    Abstract: A method for manufacturing a semiconductor device and a semiconductor device are disclosed. The method comprises forming a trench in a substrate, partially filling the trench with a first semiconductive material, forming an interface along a surface of the first semiconductive material, and filling the trench with a second semiconductive material. The semiconductor device includes a first electrode arranged along sidewalls of a trench and a dielectric arranged over the first electrode. The semiconductor device further includes a second electrode at least partially filling the trench, wherein the second electrode comprises an interface within the second electrode.
    Type: Application
    Filed: January 14, 2011
    Publication date: July 19, 2012
    Inventors: Wolfgang Lehnert, Michael Stadtmueller, Stefan Pompl, Markus Meyer
  • Publication number: 20120080690
    Abstract: According to an embodiment, a composite wafer includes a carrier substrate having a graphite core and a monocrystalline semiconductor layer attached to the carrier substrate.
    Type: Application
    Filed: September 30, 2010
    Publication date: April 5, 2012
    Applicant: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventors: Rudolf Berger, Hermann Gruber, Wolfgang Lehnert, Guenther Ruhl, Raimund Foerg, Anton Mauder, Hans-Joachim Schulze
  • Publication number: 20120083098
    Abstract: According to an embodiment, a composite wafer includes a carrier substrate having a graphite layer and a monocrystalline semiconductor layer attached to the carrier substrate.
    Type: Application
    Filed: August 9, 2011
    Publication date: April 5, 2012
    Applicant: Infineon Technologies AG
    Inventors: Rudolf Berger, Hermann Gruber, Wolfgang Lehnert, Guenther Ruhl, Raimund Foerg, Anton Mauder, Hans-Joachim Schulze, Karsten Kellermann, Michael Sommer, Christian Rottmair, Roland Rupp
  • Patent number: 7947569
    Abstract: A method for producing a semiconductor including a material layer. In one embodiment a trench is produced having two opposite sidewalls and a bottom, in a semiconductor body. A foreign material layer is produced on a first one of the two sidewalls of the trench. The trench is filled by epitaxially depositing a semiconductor material onto the second one of the two sidewalls and the bottom of the trench.
    Type: Grant
    Filed: June 30, 2008
    Date of Patent: May 24, 2011
    Assignee: Infineon Technologies Austria AG
    Inventors: Anton Mauder, Frank Pfirsch, Rudolf Berger, Stefan Sedlmaier, Wolfgang Lehnert, Raimund Foerg
  • Publication number: 20100273307
    Abstract: A method for making a device including a capacitive structure is disclosed. One embodiment provides a carrier layer having a surface. A first dielectric layer is formed on the surface. A silicon layer including silicon grains is formed on the first dielectric layer using a deposition process. A second dielectric layer is formed on the second silicon layer. A layer of an electrically conductive material is formed on the dielectric layer. A temperature process for heating at least the first dielectric layer is performed. The temperature and duration of the temperature process is selected such that the first dielectric layer is modified so that the silicon layer is electrically connected to the carrier layer.
    Type: Application
    Filed: April 27, 2009
    Publication date: October 28, 2010
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Stefan Sedlmaier, Wolfgang Lehnert, Klemens Pruegl
  • Publication number: 20090325361
    Abstract: A method for producing a semiconductor including a material layer. In one embodiment a trench is produced having two opposite sidewalls and a bottom, in a semiconductor body. A foreign material layer is produced on a first one of the two sidewalls of the trench. The trench is filled by epitaxially depositing a semiconductor material onto the second one of the two sidewalls and the bottom of the trench.
    Type: Application
    Filed: June 30, 2008
    Publication date: December 31, 2009
    Applicant: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventors: Anton Mauder, Frank Pfirsch, Rudolf Berger, Stefan Sedlmaier, Wolfgang Lehnert, Raimund Foerg
  • Publication number: 20090122460
    Abstract: A semiconductor device includes a semiconductor layer with a first electrode formed by a sintered, conductive, porous granulate and formed in or on the semiconductor layer or in or on at least one insulating layer arranged on the semiconductor layer; furthermore dielectric material covering the surface of the sintered, conductive, porous granulate, and a second electrode at least partially covering the dielectric material, wherein the dielectric material electrically insulates the second electrode from the first electrode.
    Type: Application
    Filed: November 12, 2007
    Publication date: May 14, 2009
    Inventors: Alexander Gschwandtner, Stefan Pompl, Wolfgang Lehnert, Raimund Foerg