Abstract: A method of patterning a magnetic tunnel junction (MTJ) stack is provided. According to such method, an MTJ stack is formed having a free layer, a pinned layer and a tunnel barrier layer disposed between the free layer and the pinned layer. A first area of the MTJ stack is masked while the free layer of the MTJ is exposed in a second area. The free layer is then rendered electrically and magnetically inactive in the second area.

Abstract: Methods of manufacturing MTJ memory cells and structures thereof. A diffusion barrier is disposed between an anti-ferromagnetic layer and a pinned layer of an MTJ memory cell to improve thermal stability of the MTJ memory cell. The diffusion barrier may comprise an amorphous material or a NiFe alloy. An amorphous material may be disposed adjacent a bottom surface of a tunnel junction, within a free layer, or both. An MTJ memory cell with improved thermal stability and decreased Neel coupling is achieved.

Abstract: A memory and method of making a memory is disclosed. In one embodiment, the memory includes a cap structure for a magnetoresistive random access memory device including an etch stop layer formed over an upper magnetic layer of a magnetoresistive junction (MTJ/MCJ) layered structure and a hardmask layer formed over said etch stop layer, wherein said etch stop layer is selected from a material such that an etch chemistry used for removing said hardmask layer has selectivity against etching said etch stop layer material. In a method of opening the hardmask layer, an etch process to remove exposed portions of the hardmask layer is implemented, where the etch process terminates on the etch stop layer.

Abstract: A method for writing to the magnetoresistive memory cells of a MRAM memory, includes applying write currents respectively onto a word line and a bit line. A superposition of the magnetic fields generated by the write currents in each memory cell selected by the corresponding word lines and bits lines alter a direction of the magnetization thereof. According to the method, the write currents are applied in a chronologically offset manner, to the corresponding word line and the bit line whereby the direction of magnetization of the selected memory cell is rotated in several consecutive steps in the desired direction for writing a logical “0” or “1”.

Abstract: Methods of forming ferromagnetic liners on the top surface and sidewalls of conductive lines of magnetic memory devices. The ferromagnetic liners increase the flux concentration of current run through the conductive lines, reducing the amount of write current needed to switch magnetic memory cells. In one embodiment, an in-bound pole is formed at the bottom edge of conductive lines, further concentrating the flux.

Abstract: A magneto resistive memory device is fabricated by etching a blanket metal stack comprised of a buffer layer, pinned magnetic layer, a tunnel barrier layer and a free magnetic layer. The problem of junction shorting from resputtered metal during the etching process is eliminated by formation of a protective spacer covering the side of the freelayer and tunnel barrier interface. The spacer is formed following the first etch through the free layer which stops on the barrier layer. After spacer formation a second etch is made to isolate the device. The patterning of the device tunnel junction is made using a disposable mandrel method that enables a self-aligned contact to be made following the completion of the device patterning process.

Abstract: A method of forming a magnetic stack and a structure for a magnetic stack of a resistive memory device. A crystallization inhibiting layer is formed over the free layer of a magnetic stack, improving thermal stability. The crystallization inhibiting layer comprises an amorphous material having a higher crystallization temperature than the crystallization temperature of the free layer material. The crystallization inhibiting layer inhibits the crystallization of the underlying free layer, providing improved thermal stability for the resistive memory device.

Abstract: A method of forming a magnetic stack and a structure for a magnetic stack of a resistive memory device. A crystallization inhibiting layer is formed over the free layer of a magnetic stack, improving thermal stability. The crystallization inhibiting layer comprises an amorphous material having a higher crystallization temperature than the crystallization temperature of the free layer material. The crystallization inhibiting layer inhibits the crystallization of the underlying free layer, providing improved thermal stability for the resistive memory device.

Abstract: A method of patterning a magnetic tunnel junction (MTJ) stack is provided. According to such method, an MTJ stack is formed having a free layer, a pinned layer and a tunnel barrier layer disposed between the free layer and the pinned layer. A first area of the MTJ stack is masked while the free layer of the MTJ is exposed in a second area. The free layer is then rendered electrically and magnetically inactive in the second area.

Abstract: An annular microstructure element, in particular an annularly arranged monolayer or multilayer thin film, is formed over a substrate (S), e.g., for use in a magnetoresistive memory. To that end, a masking layer is applied over the substrate. An opening (C) is etched into the masking layer, so that a partial region of the surface is uncovered. The etching operation is performed in such a way that the opening (C) is formed with an overhang (B). The overhang at least partially shades the uncovered surface from an incident particle beam (TS). A particle beam (TS) is directed at the substrate (S) at an oblique angle (?) of incidence. In this case, the substrate (S) is rotated relative to the directed particle beam (TS). From the particle beam, material is thereby deposited annularly on the uncovered surface for the purpose of forming a hole-like microstructure element (R).

Abstract: Methods of manufacturing MTJ memory cells and structures thereof. A diffusion barrier is disposed between an anti-ferromagnetic layer and a pinned layer of an MTJ memory cell to improve thermal stability of the MTJ memory cell. The diffusion barrier may comprise an amorphous material or a NiFe alloy. An amorphous material may be disposed adjacent a bottom surface of a tunnel junction, within a free layer, or both. An MTJ memory cell with improved thermal stability and decreased Neel coupling is achieved.

Abstract: A method (and structure) of thermally treating a magnetic layer of a wafer, includes annealing, for a predetermined short duration, a magnetic layer of a single wafer.

Abstract: An improved scalable, resistive element for use in a semiconductor device that can be produced with a small feature size and precise resistance is provided by the present invention. The resistive element includes a base layer positioned on top of a metal line. A seed layer of is deposited on top of the base layer. A thin barrier layer of Al is deposited on top of the seed layer and oxidized. A non-magnetic metal layer is then deposited on top of the barrier layer. The base layer and the non-magnetic metal layer form electrodes on either side of the barrier layer. The barrier layer is thin enough that a tunneling current can travel between the electrodes. The resulting resistive element may be constructed with a high resistance and a very small feature size.

Abstract: A magnetic random access memory device having a magnetic tunnel junction is provided, as well as methods of fabricating the same. The magnetic tunnel junction includes a first magnetic layer, a second magnetic layer, a tunnel barrier layer, and dielectric material portions. The first magnetic layer is formed over the second magnetic layer. The tunnel barrier layer is located between the first and second magnetic layers. The dielectric material portions are formed on sidewalls of the first magnetic layer and over the second magnetic layer. The dielectric material portions may be formed directly atop the second magnetic layer. In another embodiment, the dielectric material portion may be formed directly atop the tunnel barrier layer. Preferably, the dielectric material portions prevent shorts from developing across the tunnel barrier layer during the etching of the second magnetic layer.

Abstract: A resistive memory element (144), magnetic random access memory (MRAM) device, and methods of manufacturing thereof, wherein a thin oxide layer (132) is disposed within the first metal layer (136) of the memory element (144). The thin oxide layer (132) comprises an oxygen mono-layer. The roughness of subsequently-formed layers (134/118/116) is reduced, and magnetic capabilities of the resistive memory element (144) are enhanced by the use of the thin oxide layer (132) within the first metal layer (136).

Abstract: A resistive memory element (144), magnetic random access memory (MRAM) device, and methods of manufacturing thereof, wherein a thin oxide layer (132) is disposed within the first metal layer (136) of the memory element (144). The thin oxide layer (132) comprises an oxygen mono-layer. The roughness of subsequently-formed layers (134/118/116) is reduced, and magnetic capabilities of the resistive memory element (144) are enhanced by the use of the thin oxide layer (132) within the first metal layer (136).

Abstract: An MRAM device (200) and method of manufacturing thereof having second conductive lines (228) with a narrow width. The second conductive lines (228) partially contact the resistive memory elements (214), reducing leakage currents in neighboring cells (214).