Abstract: Topological superconductor devices with gates formed in two gate layers are described. A topological superconductor device includes a superconducting wire having a first junction near a first end of the superconducting wire and a second junction near a second end, opposite to the first end. The topological superconductor device further includes: (1) a first side-plunger gate and a second-side plunger gate formed in a first gate layer of the topological superconductor device, (2) a middle-plunger gate formed in the first gate layer of the topological superconductor device, (3) a first cutter gate formed in a second layer, different from the first layer, of the topological superconductor device, and (4) a second cutter gate formed in the second layer of the topological superconductor device. The plunger gates are operable to tune respective sections of the superconducting wire and the cutter gates are operable to open and close the respective junctions.

Abstract: A modular reactor configuration for the production of hydrogen (H2) by means of electrolysis in its single-stage design and of methane (CH4) in its two-stage design with optional gas storage and gas utilization in fuel cells, wherein the single-stage design, consisting of the electrolyzer, the fuel cell, the gas storage tanks for separate storage of H2 and oxygen (O2), the associated lines, the condenser, the H2O container, the heat storage tanks and the evaporator, is based on the principles of a reversible product cycle for H2 according to FIG. 1 and can serve both as electricity storage and for H2 production as fuel gas, and whose two-stage design, exemplified according to FIG.

Abstract: A method to evaluate a semiconductor-superconductor heterojunction for use in a qubit register of a topological quantum computer includes (a) measuring one or both of a radio-frequency (RF) junction admittance of the semiconductor-superconductor heterojunction and a sub-RF conductance including a non-local conductance of the semiconductor-superconductor heterojunction, to obtain mapping data and refinement data; (b) finding by analysis of the mapping data one or more regions of a parameter space consistent with an unbroken topological phase of the semiconductor-superconductor heterojunction; and (c) finding by analysis of the refinement data a boundary of the unbroken topological phase in the parameter space and a topological gap of the semiconductor-superconductor heterojunction for at least one of the one or more regions of the parameter space.

Abstract: Examples described in this disclosure relate to gating a semiconductor layer into a quantum spin Hall insulator state, Certain examples further relate to using quantum spin Hall insulators as topological quantum qubits. Quantum spin Hall systems may rely upon the quantum spin Hall effect by causing a state of a matter to change from a certain phase to an inverted bandgap phase. In one example, the present disclosure relates to a device including a semiconductor layer comprising an active material. The device further includes a gate coupled to the semiconductor layer, where the semiconductor layer is operable in a quantum spin Hall insulator state by using electrons and holes from the active material in response to an application of an electric field to the semiconductor layer via the gate.

Abstract: Various embodiments of the present disclosure are directed to test stands for generating test runs on the basis of a test drive using a vehicle along a driving route. In some embodiments, a test stand determines at least one idle operating time of an internal combustion engine and/or at least one overrun operating time of the internal combustion engine from a time curve of a vehicle speed and a time curve of a gas pedal position. The test stand may further set a specified idle control mode instead of the operating control mode during an idle operating time and/or a specified overrun control mode is set instead of the operating control mode during an overrun operating time in the test stand automation unit in order to carry out the test run.

Abstract: The present invention relates to a method for operating a driver model for controlling a vehicle. The driver model comprises a vehicle module (203) which determines an accelerator pedal position to be set on the vehicle. In addition, the vehicle module (203) determines a required power as a component of a total power, which total power can be generated by a drive system of the vehicle, wherein the required power corresponds to a power that is necessary for moving the vehicle at a required speed and/or a required acceleration (311) along a predefined road course. The method according to the invention further provides for a value (313) of a permissible pedal position to be assigned to the required power and for the value (313) of the permissible pedal position to be transmitted to the driver model in order to control the vehicle.

Abstract: A method to evaluate a semiconductor-superconductor heterojunction for use in a qubit register of a topological quantum computer includes (a) measuring one or both of a radio-frequency (RF) junction admittance of the semiconductor-superconductor heterojunction and a sub-RF conductance including a non-local conductance of the semiconductor-superconductor heterojunction, to obtain mapping data and refinement data; (b) finding by analysis of the mapping data one or more regions of a parameter space consistent with an unbroken topological phase of the semiconductor-superconductor heterojunction; and (c) finding by analysis of the refinement data a boundary of the unbroken topological phase in the parameter space and a topological gap of the semiconductor-superconductor heterojunction for at least one of the one or more regions of the parameter space.

Abstract: An aerial device for a vehicle, particularly an aircraft, includes an aerial arrangement and a lens, which includes a first lens area, made of a first material with a first dielectric constant, overlapping the aerial arrangement and a second lens area, made of a second material with a second dielectric constant, overlapping the first lens area, with the second dielectric constant being smaller than the first dielectric constant, and wherein the second lens area extends in a longitudinal direction and in a curve in respect of a vertical direction oriented transverse to the longitudinal direction.

Abstract: A device comprising: a portion of semiconductor; a portion of superconductor arranged to a enable a topological phase having a topological gap to be induced in a region of the semiconductor by proximity effect; and a portion of a non-magnetic material comprising an element with atomic number Z greater than or equal to 26, arranged to increase the topological gap in the topological region of the semiconductor.

Abstract: Aspects of the present disclosure are directed to estimating a gearbox gear for a test run from available measured values of a test drive. In some embodiments, a chronological sequence of a vehicle speed and an engine speed may be used as measured values, a number of areas with a linear relationship between the vehicle speed and the engine speed being identified by means of a clustering algorithm from data points from related vehicle speeds and engine speeds. The clustering algorithm, in accordance with some specific embodiments, assigns the data points to the number of areas and calculates a cluster center for each area, which is interpreted as a gear. The gear linked to the cluster center of the area is assigned to the data points of an area in order to obtain a chronological sequence of gears, and used as a target value of the test run.

Abstract: A method to evaluate a semiconductor-superconductor heterojunction for use in a qubit register of a topological quantum computer includes measuring a radio-frequency (RF) junction admittance of the semiconductor-superconductor heterojunction to obtain mapping data; finding by analysis of the mapping data one or more regions of a parameter space consistent with an unbroken topological phase of the semiconductor-superconductor heterojunction; measuring a sub-RF conductance including a non-local conductance of the semiconductor-superconductor heterojunction in each of the one or more regions of the parameter space, to obtain refinement data; and finding by analysis of the refinement data a boundary of the unbroken topological phase in the parameter space and a topological gap of the semiconductor-superconductor heterojunction for at least one of the one or more regions of the parameter space.

Abstract: A computing device, including memory storing a quantum computing device model. The quantum computing device model may include a plurality of quantum computing device components having a respective plurality of actual boundaries, including a boundary between a superconductor and a semiconductor. The computing device may further include a processor configured to receive, via an application-program interface (API), a nonuniform grid having a nonuniform spacing along at least a first spatial dimension. The processor may receive, via the API, a Schrödinger equation including a Hamiltonian having one or more operators. The processor may discretize the quantum computing device model using the nonuniform grid. The processor may compute a finite-difference solution estimate to the Schrödinger equation over the quantum computing device model as discretized with the nonuniform grid. The processor may output the finite-difference solution estimate via the API.

Abstract: A method to evaluate a semiconductor-superconductor heterojunction for use in a qubit register of a topological quantum computer includes measuring a radio-frequency (RF) junction admittance of the semiconductor-superconductor heterojunction to obtain mapping data; finding by analysis of the mapping data one or more regions of a parameter space consistent with an unbroken topological phase of the semiconductor-superconductor heterojunction; measuring a sub-RF conductance including a non-local conductance of the semiconductor-superconductor heterojunction in each of the one or more regions of the parameter space, to obtain refinement data; and finding by analysis of the refinement data a boundary of the unbroken topological phase in the parameter space and a topological gap of the semiconductor-superconductor heterojunction for at least one of the one or more regions of the parameter space.

Abstract: Aspects of the present disclosure are directed to estimating a gearbox gear for a test run from available measured values of a test drive. In some embodiments, a chronological sequence of a vehicle speed and an engine speed may be used as measured values, a number of areas with a linear relationship between the vehicle speed and the engine speed being identified by means of a clustering algorithm from data points from related vehicle speeds and engine speeds. The clustering algorithm, in accordance with some specific embodiments, assigns the data points to the number of areas and calculates a cluster center for each area, which is interpreted as a gear. The gear linked to the cluster center of the area is assigned to the data points of an area in order to obtain a chronological sequence of gears, and used as a target value of the test run.

Abstract: A semiconductor-superconductor hybrid device comprises a semiconductor, a superconductor, and a barrier between the superconductor and the semiconductor. The device is configured to enable energy level hybridisation between the semiconductor and the superconductor. The barrier is configured to increase a topological gap of the device. The barrier allows for control over the degree of hybridisation between the semiconductor and the superconductor. Further aspects provide a quantum computer comprising the device, a method of manufacturing the device, and a method of inducing topological behaviour in the device.

Abstract: A semiconductor-superconductor hybrid device comprises a semiconductor layer and a superconductor layer. The superconductor layer is arranged over an edge of the semiconductor layer so as to enable energy level hybridisation between the semiconductor layer and the superconductor layer. The semiconductor layer is arranged in a sandwich structure between first and second insulating layers, each insulating layer being in contact with a respective opposed face of the semiconductor layer. This configuration may allow for good control over the geometry of the semiconductor layer and may improve tolerance to manufacturing variations. The device may be useful in a quantum computer. Also provided is a method of manufacturing the device, and a method of inducing topological behaviour in the device.

Abstract: A computing device, including memory storing a quantum computing device model. The quantum computing device model may include a plurality of quantum computing device components having a respective plurality of actual boundaries, including a boundary between a superconductor and a semiconductor. The computing device may further include a processor configured to receive, via an application-program interface (API), a nonuniform grid having a nonuniform spacing along at least a first spatial dimension. The processor may receive, via the API, a Schrödinger equation including a Hamiltonian having one or more operators. The processor may discretize the quantum computing device model using the nonuniform grid. The processor may compute a finite-difference solution estimate to the Schrödinger equation over the quantum computing device model as discretized with the nonuniform grid. The processor may output the finite-difference solution estimate via the API.

Abstract: A device comprising: a portion of semiconductor; a portion of superconductor arranged to a enable a topological phase having a topological gap to be induced in a region of the semiconductor by proximity effect; and a portion of a non-magnetic material comprising an element with atomic number Z greater than or equal to 26, arranged to increase the topological gap in the topological region of the semiconductor.

Abstract: Various embodiments of the present disclosure are directed to test stands for generating test runs on the basis of a test drive using a vehicle along a driving route. In some embodiments, a test stand determines at least one idle operating time of an internal combustion engine and/or at least one overrun operating time of the internal combustion engine from a time curve of a vehicle speed and a time curve of a gas pedal position. The test stand may further set a specified idle control mode instead of the operating control mode during an idle operating time and/or a specified overrun control mode is set instead of the operating control mode during an overrun operating time in the test stand automation unit in order to carry out the test run.

Abstract: The disclosure relates to a quantum device and method of fabricating the same. The device comprises one or more semiconductor-superconductor nanowires, each comprising a length of semiconductor material and a coating of superconductor material coated on the semiconductor material. The nanowires may be formed over a substrate. In a first aspect at least some of the nanowires are full-shell nanowires with superconductor material being coated around a full perimeter of the semiconductor material along some or all of the length of the wire, wherein the device is operable to induce at least one Majorana zero mode, MZM, in one or more active ones of the full-shell nanowires. In a second aspect at least some of the nanowires are arranged vertically relative to the plane of the substrate in the finished device.