Abstract: An address-generating arrangement for a microprocessor has, in addition to its base address-generating unit, one or more address-generating expansion units, connected to the basic unity by an interface. The interface comprises one or more input data buses supplying data from the base unit to the expansion unit and an output data bus supplying data from the expansion unit to the basic unit under control of the microprocessor.

Abstract: The present invention relates to a method for controlling a sleep mode of a device in a wireless communications network or in a mobile point-to-point connection in order to turn off system components of the device, especially to turn off a medium access control (2) comprising the steps of: receiving a sleep mode information from an application module in a medium access control (2), coupled to an extended physical layer (PHY), especially to a base band (3), transferring the sleep mode information from the medium access control (2) to the base band (3), setting a sleep signal (sleep) of a power management mode (PMMode) to set one of the system components into sleep state, and, additionally, starting a predetermined first delay timer (T1) to delay the setting of the sleep state for one of the system components.

Abstract: The invention relates to a method and a system for calibrating a transmitting system (1) for transmitting data from a medium access control device (2) via a digital interface (IF1) to a physical layer (PHY) and an antenna (3) to a transmission line (4), wherein the physical layer (PHY) comprises a base band controller (5) and a data processing pipeline (6) comprising a plurality of functional blocks (FB1 to FB13), comprising the following steps: setting a calibration control register (R), thereupon, setting the transmitting system (1) to a calibration mode, wherein the transmitting system (1) generates a predetermined number of single test tones (T) and transmits the test tones (T) sequentially, and after transmission of the test tones (T), detecting the returned test tones (T) and measuring their levels, especially their power levels and the spectrum behaviour of the transmission line (4).

Abstract: The invention relates to a system for transmitting data from a medium access control device (2) via a digital interface (IF1) to a physical layer (PHY) and to an antenna (5), the physical layer (PHY) comprising a base band (4) with a base band controller (7) and a data processing pipeline (3) comprising a plurality of functional blocks (FB1 to FB 13), wherein a burst timing control block of one of all functional blocks (FB1 to FB 13) of the data processing pipeline (3) detects an end of a packet of payload data and, thereupon, sets a halt signal (STALL) for those functional blocks (FB1 to FB 13) preceding the burst timing control block (FB1 to FB 13) in the data processing pipeline (3) and starts a timer (T1) for counting a duration of a minimum inter- frame space (MIFS), wherein the burst timing control block (FB1 to FB 13) resets the halt signal (STALL) after expiration of the timer (T1). It also relates to a corresponding method.

Abstract: The invention relates to a method and a system for transmitting data from a medium access control device (2) via a digital interface (IF1) to a physical layer (4) and to an antenna (5), wherein the physical layer (4) comprises a base band (4) with a base band controller (7) and a data processing pipeline (3) comprising a plurality of functional blocks (FB1 . . . 13), comprising the steps of: detecting an end of a frame of payload data, which leaves the antenna (5), at a predetermined point (P1 to P3) within the data processing pipeline (3), especially at the end of the data processing pipeline (3), thereupon, starting a timer (T1) for delaying a de-assertion of an activity signal (PHY_ACTIVE) of the physical layer (4), and after expiration of the timer (T1), de-asserting the activity signal (PHY_ACTIVE).

Abstract: A method is provided for the functional control of program and/or data flows in digital signal processors and processors, which have respective closed and separated modules for program and data flow control, working in parallel with computers. The method enables a power-efficient adaptation of the signal processing with the applied SIMD command-type in the individual paths and minimizes the emergence of the appearance of NOP-commands with which the VLIW-architecture of the processor must be supplied. The adaptation of the signal processing is achieved by individually controlling the parallel signal processing of the processor in the data paths (DP) which respectively belong to a first and second slice. For this purpose, a single slice halt outputted from an SSM register bank switches the register clockline according to state-dependent signal processing.

Abstract: A method is provided for the functional control of program and/or data flows in digital signal processors and processors, which have respective closed and separated modules for program and data flow control, working in parallel with computers. The method enables a power-efficient adaptation of the signal processing with the applied SIMD command-type in the individual paths and minimizes the emergence of the appearance of NOP-commands with which the VLIW-architecture of the processor must be supplied. The adaptation of the signal processing is achieved by individually controlling the parallel signal processing of the processor in the data paths (DP) which respectively belong to a first and second slice. For this purpose, a single slice halt outputted from an SSM register bank switches the register clockline according to state-dependent signal processing.

Abstract: The invention relates to a method for configuring a memory with I/O support. The aim of the invention is to guarantee the processor and I/O functional units that function in time-critical conditions the appropriate priority for data access, using simple programs. To this end, an input memory area which the I/O unit can only write into and which the processor unit can only read out of and an output memory area which the I/O unit can only read out of and which the processor unit can only write into are specified in the processor.

Abstract: Methods are provided for effecting functional control of program flow and/or data flow in digital signal processors and in processors which have closed and separated modules for effecting the program and data flow control or which operate in parallel arithmetic-logic units. The methods enhance the functionality of the signal processor to such an extent that the units of the processor, without time delays, are adapted, with regard to their energy consumption, to the latest demands of signal processing. The methods provide additional possibilities for saving energy which are enabled by algorithm-related shutdown of functional units. An external hardware-related signal input into the processor or a software-related state output from the program flow in the processor may be used to trigger an interruption in the clock pulse supply for the respective functional units for the period of time during which these functional units are not used.

Abstract: A processor arrangement having a strip structure for parallel data processing is configured so that local data from the individual processing units or strips is brought together in a rapid manner. Input data, intermediate data and/or output data from various processing units are linked together in an operation which is at least partially combinatory. The data linking operation is not clock controlled. The linking of the local data from various strips in this manner reduces delays in parallel data processing in the processor arrangement. The combinatory data linking operation can provide an overall data linking outcome within an individual clock cycle.

Abstract: Finite field multiplication of first and second Galois elements having n bit places and belonging to a Galois field GF 2n described by an irreducible polynomial is performed by forming an intermediate result Z of intermediate sums of partial products of bit width 2n?2 in an addition part of a Galois multiplier. The intermediate result Z is processed in a reduction part of a Galois multiplier by modulo dividing by the irreducible polynomial, whereby after all XOR's are traversed a result E with n bits is computed.

Abstract: A processor bus arrangement including several data processing units, each connected to a line system specified as a bus. The bus includes connection units and bus segments, where the bus segments are connected to the bus in a seperable manner through the connection units. This guarantees that the functional units, arranged on the bus, carry out the information thereof, by means of the bus and may carry out an exchange independently of other functional units. Furthermore, other functional units in different groups may carry out an information exchange simultaneously, by means of the bus. As the connection units perform the function of the defined combinatory connection of the signal lines, the bus segments generate the physical connections between the connection units. This ensures that the connection units carry out the information exchange with as many connected functional units as required.

Abstract: In a data memory arrangement for a microprocessor system, in which the data memory is designed as a group memory composed of element memories in which data are storable in data groups having a plurality of elements under a group address in each instance, in order to make available a stack in which the memory space can be optimally utilized without the occurrence of memory gaps, the use is proposed of at least one memory pointer that has a group address component and an element address component. The stack memory can be operated with data words whose width is smaller than the data group width, without unutilized memory areas occurring in the stack.

Abstract: The invention relates to a method for configuring a memory with I/O support. The aim of the invention is to guarantee the processor and 110 functional units that function in time-critical conditions the appropriate priority for data access, using simple programmes. To this end, an input memory area which the 110 unit can only write into and which the processor unit can only read out of and an output memory area which the 110 unit can only read out of and which the processor unit can only write into are specified in the processor.

Abstract: The invention relates to an arrangement for the configuration of data paths, in which different functional units are connected to a linker unit and arranged within a CPU architecture. The aim of the invention is to permit functional extensions within the CPU architecture without essentially extending the networking complexity between the functional units and the controlling register of the CPU. Said aim is achieved, whereby the linking unit essentially comprises a processor bus arrangement and functional units with dedicated input registers and output registers.

Abstract: The invention relates to an apparatus to control data flow for a processing unit having a plurality of data paths and a plurality of parallel processing units. Each computer unit of a data path is connected to an evaluating unit, which controls the acceptance of the results into the results register by setting a flag. The output of the evaluating unit is connected to one input of a logic gate, and the other input of the logic gate to the control output of the central program control unit. The output of the logic gate is connected to the control input of the output register. In this way, each evaluating unit can check the calculation by comparing the result of computation by the parallel processing unit with a preassigned value. Upon identification of nonsense values, or upon coincidence with a preassigned value, the results register may be cleared or blocked to prevent wrong or nonsense results.

Abstract: An address-generating arrangement for a microprocessor has, in addition to its base address-generating unit, one or more address-generating expansion units, connected to the basic unity by an interface. The interface comprises one or more input data buses supplying data from the basic unit to the expansion unit and an output data bus supplying data from the expansion unit to the basic unit under control of the microprocessor.

Abstract: In a data memory arrangement for a microprocessor system, in which the data memory is designed as a group memory composed of element memories in which data are storable in data groups having a plurality of elements under a group address in each instance, in order to make available a stack in which the memory space can be optimally utilized without the occurrence of memory gaps, the use is proposed of at least one memory pointer that has a group address component and an element address component. The stack memory can be operated with data words whose width is smaller than the data group width, without unutilized memory areas occurring in the stack.

Abstract: Finite field multiplication of first and second Galois elements having n bit places and belonging to a Galois field GF 2n described by an irreducible polynomial is performed by forming an intermediate result Z of intermediate sums of partial products of bit width 2n−2 in an addition part of a Galois multiplier. The intermediate result Z is processed in a reduction part of a Galois multiplier by modulo dividing by the irreducible polynomial, whereby after all XOR's are traversed a result E with n bits is computed.