Abstract: An electrostatic discharge protection network comprising electrostatic discharge (ESD) clamp devices distributed between turns of a coil shaped inductor. The inductance of the coil shaped inductor and parasitic capacitance of the ESD clamp devices form a low pass filter structure having a very high cut-off frequency. Below the low pass filter cutoff frequency, the capacitive influence of the ESD clamp devices are cancelled by the series inductance of the coil shaped inductor. The turns of the coil shaped inductor may be fabricated on insulation layers proximate to one another so as to achieve close magnetic coupling there between, thereby achieving a larger inductance value for a given sized coil structure. Improved input and output impedance matching is also achieved by adjusting the inductive and capacitive components of the low pass filter structure formed by the coil shaped inductor and capacitance of the ESD clamp devices.

Abstract: A wireless local area network transceiver, an integrated circuit chip, a PLL (Phase Locked Loop) device and a method are provided that may reduce influences of switching noise. The frequency of an output signal of the PLL device is divided in a prescaler of the PLL device by a prescaler factor. The prescaler is operable in at least two modes with each mode having assigned a different prescaler factor. An accumulator is implemented in the PLL circuit for generating a mode switching signal for changing the mode of the prescaler. The generation of the mode switching signal is done by storing an accumulator value and processing a modulus function for updating the accumulator value. The provided technique may allow for reducing disturbances caused by switching the mode of the prescaler in the PLL circuit.

Abstract: The invention provides a harmonic direct conversion mixer having a multiplier circuit comprising first and second mixers and a generator for generating two first and two second control signals for controlling the first and second mixers. The control signals are balanced signals and are provided in four phases shifted by ?/2 in phase. The frequency of the control signals is different from the frequency of the mixer input signal.

Abstract: A dual band WLAN (Wireless Local Area Network) communications technique is provided where a frequency synthesizer unit generates an LO (Local Oscillator) signal at a frequency between both frequency bands and two downconversion units and/or two upconversion units are provided. One of the units performs conversion between the LO signal and an IF (Intermediate Frequency) signal while the other conversion takes place between the IF signal and a zero-IF or low-IF signal. Signal processing is performed on the zero-IF or low-IF signal.

Abstract: An equalizing device with notch compensation for a direct conversion receiver is disclosed. The baseband signal of a direct conversion receiver comprises a notch in the frequency response after the required DC compensation is performed. A bandpass generates a notch compensation signal on from a decision signal and a interference compensation signal of a decision feedback loop. Therefore, the reliability of the decision signal is enhanced and allows an improved data rate in WLAN applications.

Abstract: A digitally controlled filter tuning method and corresponding WLAN (Wireless Local Area Network) communication devices and integrated circuit chips are provided. A WLAN communication signal is filtered by a tunable filter. A cut-off frequency of the tunable filter is tuned by a feedback loop. Tuning the cut-off frequency includes comparing by a comparator an output signal emitted by the tunable filter to a reference signal and emitting by the comparator a comparator signal indicative of the difference between the output signal and the reference signal. Further, tuning the cut off frequency comprises receiving the comparator signal by a tuning controller and setting by the tuning controller the cut-off frequency of the tunable filter based on the comparator signal by applying a digital tuning word to the tunable filter. The described filter tuning technique may reduce product and manufacturing costs while providing enhanced tuning accuracy.

Abstract: A frequency synthesizer usable in a wireless communication device is disclosed that may ensure a low phase noise and an improved performance. The frequency synthesizer has a phase locked loop comprising a controllable oscillator generating an output signal with an output frequency that can be adjusted within a predefined frequency range dependent on the value of a first control signal. A phase/frequency detector generates an error signal in response to a phase and/or frequency difference between an input signal generated by frequency dividing said output signal, and a reference signal. A loop filter generates the first control signal based on said error signal and outputs same to the controllable oscillator. A control unit generates a second control signal from the loop filter signal and provides the second control signal to the controllable oscillator, which is arranged for modifying the predefined frequency range based on the second control signal.

Abstract: A WLAN transmitter capable of transmitting data signals modulated in accordance with an individual one of at least two different modulation schemes and corresponding methods and integrated circuit chips are provided. The WLAN transmitter contains a front end section having a low-IF topology and including a digital front end unit and an analog front end unit. The digital front end unit contains a first signal processing branch for processing transmission data signals modulated in accordance with a first one of said at least two different modulation schemes. The digital front end unit further contains a second signal processing branch for processing transmission data signals modulated in accordance with a second one of said at least two different modulation schemes. The analog front end unit contains one single signal processing branch for processing transmission data signals modulated in accordance with any one of said at least two different modulation schemes.

Abstract: In a direct conversion radio frequency receiver, an automatic gain control is implemented that allows changing the operation mode of a filter unit in the baseband section of the receiver such that in a first operation mode filter capacities are selected to provide desired output signal characteristics, whereas in a second operation mode the filter settling time is significantly reduced in order to speed up gain adaptation and to improve gain loop stability. In one embodiment the cut-off frequency of a high pass filter and the Q-factor of a subsequent low pass filter are increased and decreased respectively upon changing the gain setting of a variable gain amplifier to accelerate settling of the filter.

Abstract: A digitally controlled filter tuning method and corresponding WLAN (Wireless Local Area Network) communication devices and integrated circuit chips are provided. A WLAN communication signal is filtered by a tunable filter. A cut-off frequency of the tunable filter is tuned by a feedback loop. Tuning the cut-off frequency includes comparing by a comparator an output signal emitted by the tunable filter to a reference signal and emitting by the comparator a comparator signal indicative of the difference between the output signal and the reference signal. Further, tuning the cut-off frequency comprises receiving the comparator signal by a tuning controller and setting by the tuning controller the cut-off frequency of the tunable filter based on the comparator signal by applying a digital tuning word to the tunable filter. The described filter tuning technique may reduce product and manufacturing costs while providing enhanced tuning accuracy.

Abstract: The invention provides a mixer comprising a multiplier circuit having a first and a second mixer, a generator for generating two first and two second control signals for controlling the first and second mixers, wherein the first and second control signals are in each case balanced signals and the first control signals have a frequency f1 and the second control signals have a different frequency f2.

Abstract: A WLAN (Wireless Local Area Network) communication device comprising a WLAN frequency synthesizer for generating a synthesizer signal suitable for modulating a transmission signal and/or demodulating a reception signal and corresponding methods and integrated circuit chips are provided. The WLAN frequency synthesizer comprises a reference oscillator for generating a first reference clock signal, a fractional-N PLL (Phase-Locked Loop) unit for receiving a second reference clock signal and converting the second reference clock signal into the synthesizer signal, and a frequency multiplier for receiving the first reference clock signal and converting the first reference clock signal into the second reference clock signal to be forwarded to the fractional-N PLL unit by multiplying the frequency of the first reference clock signal by a multiplication factor. Embodiments may provide shorter settling times and/or enhanced spurious suppression of the fractional-N PLL unit.

Abstract: A mixer circuit is provided for receiving first and second input signals to be mixed and for producing a mixed output signal. The mixer circuit comprises a pair of switching transistors each of which having first, second and third terminals. The mixer circuit further comprises a single ended input connected to the first terminals of the pair of switching transistors, a local oscillator input connected to the second terminals of the pair of switching transistors for controlling the switching of the transistors, a serial capacitor connected in serial connection between the single ended input and the first terminals of the pair of switching transistors, a pair of output capacitors each of which being connected to a third terminal of the pair of switching transistors. Said third terminals of said pair of switching transistors forming an output port. The mixer circuit provides a mixer schematic with improved noise performance.

Abstract: A header detection technique for WLAN (Wireless Local Area Network) receivers is provided. The WLAN receiver comprises a signal processing unit that has analog circuitry and digital circuitry. There is further provided a header detection circuit for detecting a header in a received signal. The header detection circuit is comprised in the analog circuitry. In an embodiment, digital circuitry may be woken up based on a header detect signal that is generated by the header detection circuit. The embodiments may reduce the power consumption of the receiver, and the false detection rate.

Abstract: In one embodiment, an apparatus comprises a first integrated circuit and a second integrated circuit configured to be coupled to the first integrated circuit. The first integrated circuit comprises transceiver hardware configured to transmit and receive analog signals, one or more analog to digital converters coupled to the transceiver hardware, and one or more digital to analog converters coupled to the transceiver hardware. The analog to digital converters are configured to convert one or more received analog signals from the transceiver hardware to one or more received digital signals. The digital to analog converters are coupled to receive one or more transmitted digital signals, and are configured to convert the transmitted digital signals to transmitted analog signals for transmission by the transceiver hardware. The second integrated circuit comprises a baseband processor configured to process the received digital signals and to generate the transmitted digital signals.

Abstract: A receiver is provided for receiving a digitally modulated signal in a communication system. The receiver comprises a signal input unit adapted for determining at least one in-phase and at least one quadrature-phase value of the received signal. The receiver further comprises a signal generator connected to receive the in-phase and quadrature-phase values and to generate at least one modified in-phase value and at least one modified quadrature-phase value of a rotated phase constellation system. The receiver further comprises a signal processing unit that is adapted for processing the received signal dependent on the in-phase and quadrature-phase values and the modified in-phase and quadrature-phase values. The signal generator is a passive impedance network. Further, a corresponding integrated circuit chip and operation method are provided. Using a passive impedance network may simplify the hardware implementation by avoiding the need to provide an active amplifier.

Abstract: A FET square multiplier is disclosed that transforms an input signal into two currents I1 and I2, the difference of which is proportional to the square of the input signal. A first and a second FET are connected at their drains and are source-coupled to the source of a third FET whose transconductance is twice the transconductance of the first and the second FET. The common source node is biased by a constant current source. The FETs are operated in the saturation region to exploit the square dependency of the drain current on the difference of the gate-source voltage and the treshold voltage of an FET.

Abstract: A technique for measuring peak voltages is provided that may be used in RF transceivers or receivers of wireless local area network systems. In an apparatus for measuring a peak value of an analog voltage, an analog to digital converter is connected to receive an input voltage. A voltage level detection unit detects a voltage level of a received input voltage, and a digital memory receives and stores the detected voltage level. The digital memory updates the stored voltage level only if the currently detected voltage level is higher, or lower, than the stored level. A digital code is output that corresponds to the stored voltage level. The provided technique may allow for a more simple and less complex implementation.

Abstract: A package for packaging a semiconductor die is provided that increases the reliability of packaged semiconductor circuits in particular in high frequency applications where both analog and digital signals are used. The package comprises a first die attach paddle which is connectable to a first part of a bottom surface of the semiconductor die, and a second die attach paddle which is connectable to a second part of the bottom surface of the semiconductor die. The first and second die attach paddles are each made of an electrically conductive material, and are electrically separated from each other. Further, a corresponding semiconductor device and a method of fabricating a package and packaging a semiconductor die are provided. When packaging dies having analog and digital circuits, separate grounds not only on the chip but also in the package can be achieved so that cross talking problems can be effectively reduced.

Abstract: A PLL frequency synthesizer able to automatically set an appropriate operating mode of the voltage controlled oscillator is provided. The voltage controlled oscillator is operable in a plurality of operating modes each defining a different operating frequency range of the voltage controlled oscillator. The appropriate operating mode is selected based on an error signal detected by a phase/frequency detector of the PLL frequency synthesizer. A window comparator is used for switching to adjacent operating modes if the error signal exceeds or falls below predefined upper and lower error voltage limits.