Abstract: An equalizing device with notch compensation for a direct conversion receiver is disclosed. The baseband signal of a direct conversion receiver comprises a notch in the frequency response after the required DC compensation is performed. A bandpass generates a notch compensation signal on from a decision signal and a interference compensation signal of a decision feedback loop. Therefore, the reliability of the decision signal is enhanced and allows an improved data rate in WLAN applications.

Abstract: Direct sequence spread spectrum encoder and method for digital information in wireless LANs are provided. The encoder comprises a spreading means for mapping two input data bits to one sequence out of four selectable, nearly orthogonal sequences being selected from 216 possible sequences. The encoder further comprises a digital-to-analog converter connected to an output of the spreading means for generating an analog signal based on the symbols as outputted by the spreading means and a low-pass filter connected to an output of the digital-to-analog converter for low-pass filtering the analog signal.

Abstract: A frequency synthesizer usable in a wireless communication device is disclosed that may ensure a low phase noise and an improved performance. The frequency synthesizer has a phase locked loop comprising a controllable oscillator generating an output signal with an output frequency that can be adjusted within a predefined frequency range dependent on the value of a first control signal. A phase/frequency detector generates an error signal in response to a phase and/or frequency difference between an input signal generated by frequency dividing said output signal, and a reference signal. A loop filter generates the first control signal based on said error signal and outputs same to the controllable oscillator. A control unit generates a second control signal from the loop filter signal and provides the second control signal to the controllable oscillator, which is arranged for modifying the predefined frequency range based on the second control signal.

Abstract: A mixer circuit is provided for receiving first and second input signals to be mixed and for producing a mixed output signal. The mixer circuit comprises a pair of switching transistors each of which having first, second and third terminals. The mixer circuit further comprises a single ended input connected to the first terminals of the pair of switching transistors, a local oscillator input connected to the second terminals of the pair of switching transistors for controlling the switching of the transistors, a serial capacitor connected in serial connection between the single ended input and the first terminals of the pair of switching transistors, a pair of output capacitors each of which being connected to a third terminal of the pair of switching transistors. Said third terminals of said pair of switching transistors forming an output port. The mixer circuit provides a mixer schematic with improved noise performance.

Abstract: A technique for measuring peak voltages is provided that may be used in RF transceivers or receivers of wireless local area network systems. An apparatus is provided for measuring a peak value of an analog voltage. The apparatus comprises an analog to digital converter that is connected to receive an input voltage. The analog to digital converter comprises a voltage level detection unit that detects a voltage level of the received input voltage, and a digital memory that is connected for receiving and storing the detected voltage level. The digital memory is adapted for updating the stored voltage level only if the currently detected voltage level is higher, or lower, than the stored level. A digital code is output that corresponds to the stored voltage level. The provided technique may allow for a more simple and less complex implementation.

Abstract: A wireless local area network transceiver, an integrated circuit chip, a PLL (Phase Locked Loop) device and a method are provided that may reduce influences of switching noise. The frequency of an output signal of the PLL device is divided in a prescaler of the PLL device by a prescaler factor. The prescaler is operable in at least two modes with each mode having assigned a different prescaler factor. An accumulator is implemented in the PLL circuit for generating a mode switching signal for changing the mode of the prescaler. The generation of the mode switching signal is done by storing an accumulator value and processing a modulus function for updating the accumulator value. The provided technique may allow for reducing disturbances caused by switching the mode of the prescaler in the PLL circuit.

Abstract: A receiver, an integrated circuit chip and a method are provided for estimating the power of a digitally modulated signal received by the receiver in a communication system. The method comprises determining in-phase and quadrature-phase values of a phase constellation system relating to the received signal, calculating at least one modified in-phase value and at least one modified quadrature-phase value relating to the phase constellation system rotated by a predetermined angle, and determining absolute values of the in-phase and quadrature-phase values and the modified in-phase and quadrature-phase values. The method further comprises identifying the maximum of the absolute values, and determining a power estimate of the received signal based on the identified maximum value. The provided technique may allow for estimating the power of a digitally modulated signal in a simple and less complex implementation.

Abstract: A receiver is provided for receiving a digitally modulated signal in a communication system. The receiver comprises a signal input unit adapted for determining at least one in-phase and at least one quadrature-phase value of the received signal. The receiver further comprises a signal generator connected to receive the in-phase and quadrature-phase values and to generate at least one modified in-phase value and at least one modified quadrature-phase value of a rotated phase constellation system. The receiver further comprises a signal processing unit that is adapted for processing the received signal dependent on the in-phase and quadrature-phase values and the modified in-phase and quadrature-phase values. The signal generator is a passive impedance network. Further, a corresponding integrated circuit chip and operation method are provided. Using a passive impedance network may simplify the hardware implementation by avoiding the need to provide an active amplifier.

Abstract: A PLL frequency synthesizer able to automatically set an appropriate operating mode of the voltage controlled oscillator is provided. The voltage controlled oscillator is operable in a plurality of operating modes each defining a different operating frequency range of the voltage controlled oscillator. The appropriate operating mode is selected based on an error signal detected by a phase/frequency detector of the PLL frequency synthesizer. A window comparator is used for switching to adjacent operating modes if the error signal exceeds or falls below predefined upper and lower error voltage limits.

Abstract: In a direct conversion radio frequency receiver, an automatic gain control is implemented that allows changing the operation mode of a filter unit in the baseband section of the receiver such that in a first operation mode filter capacities are selected to provide desired output signal characteristics, whereas in a second operation mode the filter settling time is significantly reduced in order to speed up gain adaptation and to improve gain loop stability. In one embodiment the cut-off frequency of a high pass filter and the Q-factor of a subsequent low pass filter are increased and decreased respectively upon changing the gain setting of a variable gain amplifier to accelerate settling of the filter.

Abstract: An automatic gain controller for transceiver elements uses a digital topology to achieve an efficient and rapid gain settling so that an output signal of the variable gain section is within a predefined range. In one embodiment, an input signal is periodically sampled and latched so as represent the gain excess of a variable gain section. An accumulator, including an adder having saturation characteristics and a latch as a feedback element, creates a number for a new gain setting so that the variable gain section may adapt to the new gain setting within one clock period. In one example, a gain range of 84 dB is controllable and settling is achieved within 3 clock periods at most.

Abstract: In the field of radio communication technology a WLAN (wireless local area network) receiver that has an AGC (automatic gain control unit) is provided, and a corresponding method of operating a WLAN receiver. In order to provide an improved WLAN receiver with a more efficient AGC unit having a reduced settling speed and a higher accuracy, a WLAN receiver is provided that comprises at least one controllable amplifier for receiving an input signal and generating an amplified input signal. The WLAN receiver further comprises an AGC controller for evaluating a signal strength of the amplified input signal and generating a control signal for controlling the gain of the controllable amplifier dependent thereon. The AGC controller is further arranged for evaluating a signal strength of the input signal and generating the control signal dependent on the signal strength of said input signal.

Abstract: An integrated circuit comprises an ESD protection circuit including an inductor coupled between an input terminal and a ground terminal at which an RF signal is applied. The inductor is designed so as to provide a sufficient current capability required in typical ESD events. Moreover, the inductance of the inductor is selected to define, in combination with any parasitic capacitance present, a resonance tank with a resonant frequency that is matched to the RF signal. Accordingly, the operating frequency of the integrated circuit is not limited by the ESD protection circuit. In a further embodiment, an output terminal is ESD protected by an inductor that is coupled to an auxiliary voltage serving to bias an output transistor. Moreover, clamping elements, such as diodes, are provided between the auxiliary voltage and the supply voltage and between the auxiliary voltage and ground potential.

Abstract: An antenna diversity method and a corresponding communication device are disclosed that may be used in wireless LAN receivers. An AGC (Automatic Gain Control) unit controls a gain when processing signals received from antennae. A periodical switching process is performed between at least two antennae. During this periodical switching process, signals from each of the antennae are received alternately. The gain obtained by processing each received signal by means of the AGC unit is monitored and the obtained gain is compared with a predetermined threshold value. When for one of the at least two antennae the gain is below the predetermined threshold value, the periodical switching process is stopped and the antenna used at the time when stopping the periodical switching process is selected. This technique may provide an improved antenna diversity of low complexity, high performance and a short settling time.

Abstract: A signal pre-processing device particularly in wireless LAN devices is provided that comprises an AGC (Automatic Gain Control) unit, an ADC (Analog-to-Digital Converting) unit and a normalization unit. The AGC unit amplifies a received analog input signal and outputs an amplified analog signal. Further, it automatically controls an amplification gain when amplifying the analog input signal. The ADC unit receives the amplified analog signal, converts it into a digital signal and outputs the digital signal. The normalization unit is receives the digital signal, applies a normalization function to the digital signal and outputs the normalized digital signal. Thus, less precise AGC units can be used, thereby reducing production costs as well as the size and complexity of the AGC unit. Further, shorter circuit development times are obtainable.

Abstract: A package for packaging a semiconductor die is provided that increases the reliability of packaged semiconductor circuits in particular in high frequency applications where both analog and digital signals are used. The package comprises a first die attach paddle which is connectable to a first part of a bottom surface of the semiconductor die, and a second die attach paddle which is connectable to a second part of the bottom surface of the semiconductor die. The first and second die attach paddles are each made of an electrically conductive material, and are electrically separated from each other. Further, a corresponding semiconductor device and a method of fabricating a package and packaging a semiconductor die are provided. When packaging dies having analog and digital circuits, separate grounds not only on the chip but also in the package can be achieved so that cross talking problems can be effectively reduced.

Abstract: An inductor and transformer comprise a plurality of interleaved conductive layers and insulation layers fabricated on a monolithic semiconductor integrated circuit die. The conductive layers are shaped into coil turns of the inductor and the transformer, and are stacked vertically (perpendicular to the horizontal plane of the coil layers) and proximate to one another so as to achieve close magnetic coupling therebetween, thereby achieving a larger inductance value for a given sized coil structure. The conductive layer coil turns are connected together with conductive vias through the interposing insulation layers.

Abstract: A FET square multiplier is disclosed that transforms an input signal into two currents I1 and I2, the difference of which is proportional to the square of the input signal. A first and a second FET are connected at their drains and are source-coupled to the source of a third FET whose transconductance is twice the transconductance of the first and the second FET. The common source node is biased by a constant current source. The FETs are operated in the saturation region to exploit the square dependency of the drain current on the difference of the gate-source voltage and the treshold voltage of an FET.