Abstract: A semiconductor device includes a die pad, a plurality of first lands each having a first land first top recessed portion disposed on a first land first end distal to the die pad, and a plurality of second lands each having a second land first bottom recessed portion disposed on a second land first end distal to the die pad. A semiconductor die is electrically connected to the first and second lands. A package body, which defines a bottom surface and a side surface, at least partially encapsulating the first and second lands and the semiconductor die such that at least portions of the first and second lands are exposed in and substantially flush with the bottom surface of the package body.

Abstract: Provided are a method for fabricating a semiconductor package and a semiconductor package using the same, which can simplify a fabricating process of the semiconductor package by forming a lead frame on which a semiconductor die can be mounted without a separate grinding process, and can improve product reliability by preventing warpage from occurring during a grinding process.

Abstract: A packaged semiconductor device includes a routable molded lead frame structure with a surface finish layer. In one embodiment, the routable molded lead frame structure includes a first laminated layer including the surface finish layer, vias connected to the surface finish layer, and a first resin layer covering the vias leaving the top surface of the surface finish layer exposed. A second laminated layer includes second conductive patterns connected to the vias, bump pads connected to the second conductive patterns, and a second resin layer covering one side of the first resin layer, the second conductive patterns and the bump pads. A semiconductor die is electrically connected to the surface finish layer and an encapsulant covers the semiconductor die and another side of the first resin layer. The surface finish layer provides a customizable and improved bonding structure for connecting the semiconductor die to the routable molded lead frame structure.

Abstract: In one embodiment, an electronic package includes a substrate having a die pad plurality of lands embedded within substrate encapsulant. An electronic chip including an electronic component is connected to the die pad. The die pad is configured with a recessed well extending from a top surface of the die pad towards a bottom surface of the die pad. The electronic component is position at least proximate to and overlapping the recessed well to increase the distance between the die pad and the electronic component. In one embodiment, the electronic component includes a passive component, such as an inductor. A package body encapsulates the electronic chip and top surfaces of the substrate, and is further disposed within the recessed well. The die pad bottom surface is continuous below the recessed well.

Abstract: In one embodiment, a semiconductor package includes a multi-layer encapsulated conductive substrate having a fine pitch. The multi-layer encapsulated conductive substrate includes a conductive leads spaced apart from each other, a first encapsulant disposed between the leads, a first conductive layer electrically connected to the plurality of leads, conductive pillars disposed on the first conductive layer, a second encapsulant encapsulating the first conductive layer and the conductive pillars, and a second conductive layer electrically connected to the conductive pillars and exposed in the second encapsulant. A semiconductor die is electrically connected to the second patterned conductive layer. A third encapsulant covers at least the semiconductor die.

Abstract: In one embodiment, a semiconductor device includes a die pad defining multiple peripheral edge segments. In addition, the semiconductor device includes a plurality of leads and lands which are provided in a prescribed arrangement. Connected to the top surface of the die pad is at least one semiconductor die which is electrically connected to at least some of the leads and lands. At least portions of the die pad, the leads, the lands, and the semiconductor die are encapsulated by the package body, with at least portions of the bottom surfaces of the die pad and the lands being exposed in a common exterior surface of the package body.

Abstract: In one embodiment, a method for fabricating a semiconductor package includes providing a multi-layer molded conductive structure. The multi-layer molded conductive structure includes a first conductive structure disposed on a surface of a carrier and a first encapsulant covering at least portions of the first conductive structure while other portions are exposed in the first encapsulant. A second conductive structure is disposed on the first encapsulant and electrically connected to the first conductive structure. A second encapsulant covers a first portion of the second conductive structure while a second portion of the second conductive structure is exposed to the outside, and a third portion of the second conductive structure is exposed in a receiving space disposed in the second encapsulant. The method includes electrically connecting a semiconductor die to the second conductive structure and in some embodiments removing the carrier.

Abstract: In one embodiment, an electronic package includes a substrate having a plurality of lands embedded within an insulating layer. Conductive patterns are disposed on at least a portion of a respective land top surface. An electronic device is electrically connected to the conductive patterns and a package body encapsulating the top surface of the insulating material and the electronic device, wherein the bottom land surfaces are exposed to the outside. In another embodiment, the top land surfaces and the top surface of the insulating layer are substantially co-planar and the conductive patterns further overlap portions of the top surface of the insulating layer.

Abstract: In one embodiment, an electronic package includes a substrate having a die pad plurality of lands embedded within substrate encapsulant. An electronic chip including an electronic component is connected to the die pad. The die pad is configured with a recessed well extending from a top surface of the die pad towards a bottom surface of the die pad. The electronic component is position at least proximate to and overlapping the recessed well to increase the distance between the die pad and the electronic component. In one embodiment, the electronic component includes a passive component, such as an inductor. A package body encapsulates the electronic chip and top surfaces of the substrate, and is further disposed within the recessed well. The die pad bottom surface is continuous below the recessed well.

Abstract: In one embodiment, a semiconductor device includes a die pad defining multiple peripheral edge segments. In addition, the semiconductor device includes a plurality of leads and lands which are provided in a prescribed arrangement. Connected to the top surface of the die pad is at least one semiconductor die which is electrically connected to at least some of the leads and lands. At least portions of the die pad, the leads, the lands, and the semiconductor die are encapsulated by the package body, with at least portions of the bottom surfaces of the die pad and the lands being exposed in a common exterior surface of the package body.

Abstract: In accordance with the present invention, there is provided a semiconductor package or device including a uniquely configured leadframe sized and configured to maximize the available number of exposed lands in the semiconductor device. More particularly, the semiconductor device of the present invention includes a die pad (or die paddle) defining multiple peripheral edge segments. In addition, the semiconductor device includes a plurality of leads and lands which are provided in a prescribed arrangement. Connected to the top surface of the die pad is at least one semiconductor die which is electrically connected to at least some of the leads and lands. At least portions of the die pad, the leads, the lands, and the semiconductor die are encapsulated by the package body, with at least portions of the bottom surfaces of the die pad and the lands being exposed in a common exterior surface of the package body.